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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id o13sm19168231edr.94.2020.12.15.14.57.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:57:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree Date: Tue, 15 Dec 2020 23:57:33 +0100 Message-Id: <20201215225757.764263-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Missing review: 1-3 14 17 19-24=0D =0D Since v1:=0D - rebased=0D - addressed Richard review comments=0D - reworded some commit descriptions=0D - avoid 64-bit ifdef'ry=0D =0D Finally, we use decodetree with the MIPS target.=0D =0D Starting easy with the MSA ASE. 2700+ lines extracted=0D from helper.h and translate.c, now built as an new=0D object: mod-msa_translate.o.=0D =0D Phil.=0D =0D Available:=0D https://gitlab.com/philmd/qemu/-/commits/mips_msa_decodetree_v2=0D =0D Based-on: <20201214183739.500368-1-f4bug@amsat.org>=0D =0D Philippe Mathieu-Daud=C3=A9 (24):=0D target/mips/translate: Extract decode_opc_legacy() from decode_opc()=0D target/mips/translate: Expose check_mips_64() to 32-bit mode=0D target/mips/cpu: Introduce isa_rel6_available() helper=0D target/mips: Introduce ase_msa_available() helper=0D target/mips: Simplify msa_reset()=0D target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA=0D target/mips: Simplify MSA TCG logic=0D target/mips: Remove now unused ASE_MSA definition=0D target/mips: Alias MSA vector registers on FPU scalar registers=0D target/mips: Extract msa_translate_init() from mips_tcg_init()=0D target/mips: Remove CPUMIPSState* argument from gen_msa*() methods=0D target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()=0D target/mips: Rename msa_helper.c as mod-msa_helper.c=0D target/mips: Move msa_reset() to mod-msa_helper.c=0D target/mips: Extract MSA helpers from op_helper.c=0D target/mips: Extract MSA helper definitions=0D target/mips: Declare gen_msa/_branch() in 'translate.h'=0D target/mips: Extract MSA translation routines=0D target/mips: Introduce decode tree bindings for MSA opcodes=0D target/mips: Use decode_ase_msa() generated from decodetree=0D target/mips: Extract LSA/DLSA translation generators=0D target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes=0D target/mips: Introduce decodetree helpers for Release6 LSA/DLSA=0D opcodes=0D target/mips/mod-msa: Pass TCGCond argument to gen_check_zero_element()=0D =0D target/mips/cpu.h | 7 +=0D target/mips/helper.h | 436 +--=0D target/mips/internal.h | 4 +-=0D target/mips/mips-defs.h | 1 -=0D target/mips/translate.h | 25 +-=0D target/mips/isa-mips32r6.decode | 17 +=0D target/mips/isa-mips64r6.decode | 17 +=0D target/mips/mod-msa32.decode | 28 +=0D target/mips/mod-msa64.decode | 17 +=0D target/mips/cpu.c | 14 +-=0D target/mips/isa-mips_rel6_translate.c | 37 +=0D target/mips/kvm.c | 12 +-=0D .../mips/{msa_helper.c =3D> mod-msa_helper.c} | 429 +++=0D target/mips/mod-msa_translate.c | 2286 ++++++++++++++++=0D target/mips/op_helper.c | 394 ---=0D target/mips/translate.c | 2352 +----------------=0D target/mips/translate_addr_const.c | 52 +=0D target/mips/cpu-defs.c.inc | 40 +-=0D target/mips/meson.build | 14 +-=0D target/mips/mod-msa_helper.h.inc | 443 ++++=0D 20 files changed, 3437 insertions(+), 3188 deletions(-)=0D create mode 100644 target/mips/isa-mips32r6.decode=0D create mode 100644 target/mips/isa-mips64r6.decode=0D create mode 100644 target/mips/mod-msa32.decode=0D create mode 100644 target/mips/mod-msa64.decode=0D create mode 100644 target/mips/isa-mips_rel6_translate.c=0D rename target/mips/{msa_helper.c =3D> mod-msa_helper.c} (93%)=0D create mode 100644 target/mips/mod-msa_translate.c=0D create mode 100644 target/mips/translate_addr_const.c=0D create mode 100644 target/mips/mod-msa_helper.h.inc=0D =0D -- =0D 2.26.2=0D =0D