[PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition

Philippe Mathieu-Daudé
2020-12-15T23:05:17Z

We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 1 -
target/mips/cpu-defs.c.inc | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..805034b8956 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -45,7 +45,6 @@
#define ASE_MT 0x0000000040000000ULL
#define ASE_SMARTMIPS 0x0000000080000000ULL
#define ASE_MICROMIPS 0x0000000100000000ULL
-#define ASE_MSA 0x0000000200000000ULL
/*
* bits 40-51: vendor-specific base instruction sets
*/
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index bf12e91f715..325b24b8e2c 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -410,7 +410,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 32,
.PABITS = 40,
- .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+ .insn_flags = CPU_MIPS32R5,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -721,7 +721,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -761,7 +761,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -887,7 +887,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A | ASE_MSA,
+ .insn_flags = CPU_LOONGSON3A,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2