Re: [RESEND v13 09/10] KVM: vmx/pmu: Expose LBR_FMT in the MSR_IA32_PERF_CAPABILITIES

Paolo Bonzini
2021-01-26T15:29:54Z

On 08/01/21 02:37, Like Xu wrote:
> Userspace could enable guest LBR feature when the exactly supported
> LBR format value is initialized to the MSR_IA32_PERF_CAPABILITIES
> and the LBR is also compatible with vPMU version and host cpu model.
>
> Signed-off-by: Like Xu <like.xu@linux.intel.com>
> Reviewed-by: Andi Kleen <ak@linux.intel.com>
> ---
> arch/x86/kvm/vmx/capabilities.h | 9 ++++++++-
> arch/x86/kvm/vmx/vmx.c | 7 +++++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
> index 57b940c613ab..a9a7c4d1b634 100644
> --- a/arch/x86/kvm/vmx/capabilities.h
> +++ b/arch/x86/kvm/vmx/capabilities.h
> @@ -378,7 +378,14 @@ static inline u64 vmx_get_perf_capabilities(void)
> * Since counters are virtualized, KVM would support full
> * width counting unconditionally, even if the host lacks it.
> */
> - return PMU_CAP_FW_WRITES;
> + u64 perf_cap = PMU_CAP_FW_WRITES;
> +
> + if (boot_cpu_has(X86_FEATURE_PDCM))
> + rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap);
> +
> + perf_cap |= perf_cap & PMU_CAP_LBR_FMT;
> +
> + return perf_cap;
> }
>
> static inline u64 vmx_supported_debugctl(void)
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index ad3b079f6700..9cb5b1e4fc27 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -2229,6 +2229,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> case MSR_IA32_PERF_CAPABILITIES:
> if (data && !vcpu_to_pmu(vcpu)->version)
> return 1;
> + if (data & PMU_CAP_LBR_FMT) {
> + if ((data & PMU_CAP_LBR_FMT) !=
> + (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
> + return 1;
> + if (!intel_pmu_lbr_is_compatible(vcpu))
> + return 1;
> + }
> ret = kvm_set_msr_common(vcpu, msr_info);
> break;
>
>

Please move this hunk to patch 4.

Paolo