From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5606EC433DB for ; Thu, 28 Jan 2021 13:27:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED03D6146D for ; Thu, 28 Jan 2021 13:27:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231465AbhA1N1i (ORCPT ); Thu, 28 Jan 2021 08:27:38 -0500 Received: from 8bytes.org ([81.169.241.247]:53438 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229950AbhA1N1h (ORCPT ); Thu, 28 Jan 2021 08:27:37 -0500 X-Greylist: delayed 513 seconds by postgrey-1.27 at vger.kernel.org; Thu, 28 Jan 2021 08:27:36 EST Received: by theia.8bytes.org (Postfix, from userid 1000) id 8407751D; Thu, 28 Jan 2021 14:18:19 +0100 (CET) Date: Thu, 28 Jan 2021 14:18:18 +0100 From: Joerg Roedel To: Lai Jiangshan Cc: X86 ML , Joerg Roedel , "H. Peter Anvin" , Andy Lutomirski , Dave Hansen , Peter Zijlstra , Jiri Slaby , Dan Williams , Tom Lendacky , Juergen Gross , Kees Cook , David Rientjes , Cfir Cohen , Erdem Aktas , Masami Hiramatsu , Mike Stunes , Sean Christopherson , Martin Radev , LKML , kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: Re: [PATCH v7 45/72] x86/entry/64: Add entry code for #VC handler Message-ID: <20210128131817.GP32671@8bytes.org> References: <20200907131613.12703-1-joro@8bytes.org> <20200907131613.12703-46-joro@8bytes.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hello Lai, On Sun, Jan 24, 2021 at 10:11:14PM +0800, Lai Jiangshan wrote: > > + > > + /* > > + * No need to switch back to the IST stack. The current stack is either > > + * identical to the stack in the IRET frame or the VC fall-back stack, > > + * so it is definitly mapped even with PTI enabled. > > + */ > > + jmp paranoid_exit > > + > > > > Hello > > I know we don't enable PTI on AMD, but the above comment doesn't align to the > next code. > > We assume PTI is enabled as the comments said "even with PTI enabled". > > When #VC happens after entry_SYSCALL_64 but before it switches to the > kernel CR3. vc_switch_off_ist() will switch the stack to the kernel stack > and paranoid_exit can't work when it switches to user CR3 on the kernel stack. > > The comment above lost information that the current stack is possible to be > the kernel stack which is mapped not user CR3. > > Maybe I missed something. You are right, the scenario above would cause problems for the current #VC entry code. With SEV-ES an #VC exception can't happen in the early syscall entry code, so I think its the best to update the comment reflecting this. In the future this might change and then the #VC entry code needs to take care of this case too. Thanks for pointing it out. Regards, Joerg