[PATCH v2 0/4] KVM: x86/pmu: Guest Architectural LBR Enabling

Like Xu
2021-02-03T14:05:54Z

Hi geniuses,

Please help review the new version of Arch LBR enabling on
KVM based on the latest kvm/queue tree.

The Architectural Last Branch Records (LBRs) is publiced
in the 319433-040 release of Intel Architecture Instruction
Set Extensions and Future Features Programming Reference[0].

The main advantages for the Arch LBR users are [1]:
- Faster context switching due to XSAVES support and faster reset of
LBR MSRs via the new DEPTH MSR
- Faster LBR read for a non-PEBS event due to XSAVES support, which
lowers the overhead of the NMI handler. (For a PEBS event, the LBR
information is recorded in the PEBS records. There is no impact on
the PEBS event.)
- Linux kernel can support the LBR features without knowing the model
number of the current CPU.

Please check more details in each commit and feel free to comment.

[0] https://software.intel.com/content/www/us/en/develop/download/
intel-architecture-instruction-set-extensions-and-future-features-programming-reference.html
[1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/

---
v1->v2 Changelog:
- rebased on the latest kvm/queue tree;
- refine some comments for guest usage;

Previous:
https://lore.kernel.org/kvm/20200731074402.8879-1-like.xu@linux.intel.com/

Like Xu (4):
KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR
KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR
KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field
KVM: x86: Expose Architectural LBR CPUID and its XSAVES bit

arch/x86/include/asm/vmx.h | 4 ++
arch/x86/kvm/cpuid.c | 23 ++++++++++
arch/x86/kvm/vmx/capabilities.h | 25 +++++++----
arch/x86/kvm/vmx/pmu_intel.c | 74 +++++++++++++++++++++++++++++++--
arch/x86/kvm/vmx/vmx.c | 15 ++++++-
arch/x86/kvm/vmx/vmx.h | 3 ++
arch/x86/kvm/x86.c | 10 ++++-
7 files changed, 140 insertions(+), 14 deletions(-)

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2.29.2