From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com,
alexandru.elisei@arm.com, suzuki.poulose@arm.com,
mark.rutland@arm.com, christoffer.dall@arm.com,
pbonzini@redhat.com, drjones@redhat.com, qperret@google.com,
kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kernel-team@android.com, tabba@google.com
Subject: [PATCH v3 05/15] KVM: arm64: Refactor sys_regs.h,c for nVHE reuse
Date: Mon, 19 Jul 2021 17:03:36 +0100 [thread overview]
Message-ID: <20210719160346.609914-6-tabba@google.com> (raw)
In-Reply-To: <20210719160346.609914-1-tabba@google.com>
Refactor sys_regs.h and sys_regs.c to make it easier to reuse
common code. It will be used in nVHE in a later patch.
Note that the refactored code uses __inline_bsearch for find_reg
instead of bsearch to avoid copying the bsearch code for nVHE.
No functional change intended.
Signed-off-by: Fuad Tabba <tabba@google.com>
---
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kvm/sys_regs.c | 30 +-----------------------------
arch/arm64/kvm/sys_regs.h | 31 +++++++++++++++++++++++++++++++
3 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7b9c3acba684..326f49e7bd42 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1153,6 +1153,9 @@
#define ICH_VTR_A3V_SHIFT 21
#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
+/* Extract the feature specified from the feature id register. */
+#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 80a6e41cadad..1a939c464858 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -44,10 +44,6 @@
* 64bit interface.
*/
-#define reg_to_encoding(x) \
- sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
- (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
-
static bool read_from_write_only(struct kvm_vcpu *vcpu,
struct sys_reg_params *params,
const struct sys_reg_desc *r)
@@ -1026,8 +1022,6 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
return true;
}
-#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
-
/* Read a sanitised cpufeature ID register by sys_reg_desc */
static u64 read_id_reg(const struct kvm_vcpu *vcpu,
struct sys_reg_desc const *r, bool raz)
@@ -2106,23 +2100,6 @@ static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
return 0;
}
-static int match_sys_reg(const void *key, const void *elt)
-{
- const unsigned long pval = (unsigned long)key;
- const struct sys_reg_desc *r = elt;
-
- return pval - reg_to_encoding(r);
-}
-
-static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
- const struct sys_reg_desc table[],
- unsigned int num)
-{
- unsigned long pval = reg_to_encoding(params);
-
- return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
-}
-
int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
{
kvm_inject_undefined(vcpu);
@@ -2365,13 +2342,8 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
trace_kvm_handle_sys_reg(esr);
- params.Op0 = (esr >> 20) & 3;
- params.Op1 = (esr >> 14) & 0x7;
- params.CRn = (esr >> 10) & 0xf;
- params.CRm = (esr >> 1) & 0xf;
- params.Op2 = (esr >> 17) & 0x7;
+ params = esr_sys64_to_params(esr);
params.regval = vcpu_get_reg(vcpu, Rt);
- params.is_write = !(esr & 1);
ret = emulate_sys_reg(vcpu, ¶ms);
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index 9d0621417c2a..cc0cc95a0280 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -11,6 +11,12 @@
#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
#define __ARM64_KVM_SYS_REGS_LOCAL_H__
+#include <linux/bsearch.h>
+
+#define reg_to_encoding(x) \
+ sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
+ (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
+
struct sys_reg_params {
u8 Op0;
u8 Op1;
@@ -21,6 +27,14 @@ struct sys_reg_params {
bool is_write;
};
+#define esr_sys64_to_params(esr) \
+ ((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
+ .Op1 = ((esr) >> 14) & 0x7, \
+ .CRn = ((esr) >> 10) & 0xf, \
+ .CRm = ((esr) >> 1) & 0xf, \
+ .Op2 = ((esr) >> 17) & 0x7, \
+ .is_write = !((esr) & 1) })
+
struct sys_reg_desc {
/* Sysreg string for debug */
const char *name;
@@ -152,6 +166,23 @@ static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
return i1->Op2 - i2->Op2;
}
+static inline int match_sys_reg(const void *key, const void *elt)
+{
+ const unsigned long pval = (unsigned long)key;
+ const struct sys_reg_desc *r = elt;
+
+ return pval - reg_to_encoding(r);
+}
+
+static inline const struct sys_reg_desc *
+find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
+ unsigned int num)
+{
+ unsigned long pval = reg_to_encoding(params);
+
+ return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
+}
+
const struct sys_reg_desc *find_reg_by_id(u64 id,
struct sys_reg_params *params,
const struct sys_reg_desc table[],
--
2.32.0.402.g57bb445576-goog
next prev parent reply other threads:[~2021-07-19 16:28 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 16:03 [PATCH v3 00/15] KVM: arm64: Fixed features for protected VMs Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 01/15] KVM: arm64: placeholder to check if VM is protected Fuad Tabba
2021-08-12 8:58 ` Will Deacon
2021-08-12 9:22 ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 02/15] KVM: arm64: Remove trailing whitespace in comment Fuad Tabba
2021-08-12 8:59 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 03/15] KVM: arm64: MDCR_EL2 is a 64-bit register Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 04/15] KVM: arm64: Fix names of config register fields Fuad Tabba
2021-07-19 16:03 ` Fuad Tabba [this message]
2021-07-20 13:38 ` [PATCH v3 05/15] KVM: arm64: Refactor sys_regs.h,c for nVHE reuse Andrew Jones
2021-07-20 14:03 ` Fuad Tabba
2021-08-12 8:59 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 06/15] KVM: arm64: Restore mdcr_el2 from vcpu Fuad Tabba
2021-07-20 14:52 ` Andrew Jones
2021-07-21 7:37 ` Fuad Tabba
2021-08-12 8:46 ` Will Deacon
2021-08-12 9:28 ` Fuad Tabba
2021-08-12 9:49 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 07/15] KVM: arm64: Track value of cptr_el2 in struct kvm_vcpu_arch Fuad Tabba
2021-08-12 8:59 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 08/15] KVM: arm64: Add feature register flag definitions Fuad Tabba
2021-08-12 8:59 ` Will Deacon
2021-08-12 9:21 ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 09/15] KVM: arm64: Add config register bit definitions Fuad Tabba
2021-08-12 8:59 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 10/15] KVM: arm64: Guest exit handlers for nVHE hyp Fuad Tabba
2021-08-03 15:32 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 11/15] KVM: arm64: Add trap handlers for protected VMs Fuad Tabba
2021-08-12 9:45 ` Will Deacon
2021-08-16 14:39 ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 12/15] KVM: arm64: Move sanitized copies of CPU features Fuad Tabba
2021-08-12 9:46 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 13/15] KVM: arm64: Trap access to pVM restricted features Fuad Tabba
2021-08-12 9:53 ` Will Deacon
2021-07-19 16:03 ` [PATCH v3 14/15] KVM: arm64: Handle protected guests at 32 bits Fuad Tabba
2021-07-19 19:43 ` Oliver Upton
2021-07-21 8:39 ` Fuad Tabba
2021-08-12 9:57 ` Will Deacon
2021-08-12 13:08 ` Fuad Tabba
2021-07-19 16:03 ` [PATCH v3 15/15] KVM: arm64: Restrict protected VM capabilities Fuad Tabba
2021-08-12 9:59 ` Will Deacon
2021-08-16 14:40 ` Fuad Tabba
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