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Fri, 1 Oct 2021 21:43:43 +0000 Date: Fri, 1 Oct 2021 22:43:40 +0100 From: Joey Gouly To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Eric Auger , Christoffer Dall , kernel-team@android.com, nd@arm.com Subject: Re: [PATCH 2/5] KVM: arm64: Work around GICv3 locally generated SErrors Message-ID: <20211001214340.GA35802@e124191.cambridge.arm.com> References: <20210924082542.2766170-1-maz@kernel.org> <20210924082542.2766170-3-maz@kernel.org> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210924082542.2766170-3-maz@kernel.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-ClientProxiedBy: LO4P123CA0034.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:151::21) To DB8PR08MB5433.eurprd08.prod.outlook.com (2603:10a6:10:118::13) MIME-Version: 1.0 Received: from e124191.cambridge.arm.com (217.140.106.50) by LO4P123CA0034.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:151::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2021 21:43:57.3888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d8d5fc5-b773-44e5-6ed6-08d98524929c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.33.187.114];Helo=[64aa7808-outbound-2.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT029.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6245 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, On Fri, Sep 24, 2021 at 09:25:39AM +0100, Marc Zyngier wrote: > The infamous M1 has a feature nobody else ever implemented, > in the form of the "GIC locally generated SError interrupts", > also known as SEIS for short. > > These SErrors are generated when a guest does something that violates > the GIC state machine. It would have been simpler to just *ignore* > the damned thing, but that's not what this HW does. Oh well. > > This part of of the architecture is also amazingly under-specified. > There is a whole 10 lines that describe the feature in a spec that > is 930 pages long, and some of these lines are factually wrong. > Oh, and it is deprecated, so the insentive to clarify it is low. > > Now, the spec says that this should be a *virtual* SError when > HCR_EL2.AMO is set. As it turns out, that's not always the case > on this CPU, and the SError sometimes fires on the host as a > physical SError. Goodbye, cruel world. This clearly is a HW bug, > and it means that a guest can easily take the host down, on demand. > > Thankfully, we have seen systems that were just as broken in the > past, and we have the perfect vaccine for it. > > Apple M1, please meet the Cavium ThunderX workaround. All your > GIC accesses will be trapped, sanitised, and emulated. Only the > signalling aspect of the HW will be used. It won't be super speedy, > but it will at least be safe. You're most welcome. > > Given that this has only ever been seen on this single implementation, > that the spec is unclear at best and that we cannot trust it to ever > be implemented correctly, gate the workaround solely on ICH_VTR_EL2.SEIS > being set. > > Signed-off-by: Marc Zyngier [...] I reproduced this issue on my M1 by using kvmtool and EDKII [1], and have confirmed that this fixes it. Tested-by: Joey Gouly Thanks, Joey [1] It is fixed in EDKII now, but I reverted Ard's EDKII commit locally: a82bad9730178a1e3a67c9bfc83412b87a8ad734