From: Lai Jiangshan <jiangshanlai@gmail.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Lai Jiangshan <laijs@linux.alibaba.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>
Subject: [PATCH 13/15] KVM: SVM: Add and use svm_register_cache_reset()
Date: Mon, 8 Nov 2021 20:44:05 +0800 [thread overview]
Message-ID: <20211108124407.12187-14-jiangshanlai@gmail.com> (raw)
In-Reply-To: <20211108124407.12187-1-jiangshanlai@gmail.com>
From: Lai Jiangshan <laijs@linux.alibaba.com>
It resets all the appropriate bits like vmx.
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
---
arch/x86/kvm/svm/svm.c | 3 +--
arch/x86/kvm/svm/svm.h | 26 ++++++++++++++++++++++++++
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index b7da66935e72..ba9cfddd2875 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -3969,8 +3969,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
vmcb_mark_all_clean(svm->vmcb);
-
- kvm_register_clear_available(vcpu, VCPU_EXREG_PDPTR);
+ svm_register_cache_reset(vcpu);
/*
* We need to handle MC intercepts here before the vcpu has a chance to
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 0d7bbe548ac3..1cf5d5e2d0cd 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -274,6 +274,32 @@ static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit)
return !test_bit(bit, (unsigned long *)&vmcb->control.clean);
}
+static inline void svm_register_cache_reset(struct kvm_vcpu *vcpu)
+{
+/*
+ * SVM_REGS_AVAIL_SET - The set of registers that will be updated in cache on
+ * demand. Other registers not listed here are synced to
+ * the cache immediately after VM-Exit.
+ *
+ * SVM_REGS_DIRTY_SET - The set of registers that might be outdated in
+ * architecture. Other registers not listed here are synced
+ * to the architecture immediately when modifying.
+ *
+ * Special case: VCPU_EXREG_CR3 should be in this set due
+ * to the fact. But KVM_REQ_LOAD_MMU_PGD is always
+ * requested when the cache vcpu->arch.cr3 is changed and
+ * svm_load_mmu_pgd() always syncs the new CR3 value into
+ * the architecture. So the dirty information of
+ * VCPU_EXREG_CR3 is not used which means VCPU_EXREG_CR3
+ * isn't required to be put in this set.
+ */
+#define SVM_REGS_AVAIL_SET (1 << VCPU_EXREG_PDPTR)
+#define SVM_REGS_DIRTY_SET (0)
+
+ vcpu->arch.regs_avail &= ~SVM_REGS_AVAIL_SET;
+ vcpu->arch.regs_dirty &= ~SVM_REGS_DIRTY_SET;
+}
+
static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
return container_of(vcpu, struct vcpu_svm, vcpu);
--
2.19.1.6.gb485710b
next prev parent reply other threads:[~2021-11-08 12:45 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-08 12:43 [PATCH 00/15] KVM: X86: Fix and clean up for register caches Lai Jiangshan
2021-11-08 12:43 ` [PATCH 01/15] KVM: X86: Ensure the dirty PDPTEs to be loaded Lai Jiangshan
2021-11-08 12:43 ` [PATCH 02/15] KVM: VMX: Mark VCPU_EXREG_PDPTR available in ept_save_pdptrs() Lai Jiangshan
2021-11-08 12:43 ` [PATCH 03/15] KVM: SVM: Always clear available of VCPU_EXREG_PDPTR in svm_vcpu_run() Lai Jiangshan
2021-11-08 12:43 ` [PATCH 04/15] KVM: VMX: Add and use X86_CR4_TLB_BITS when !enable_ept Lai Jiangshan
2021-11-18 15:18 ` Paolo Bonzini
2021-11-08 12:43 ` [PATCH 05/15] KVM: VMX: Add and use X86_CR4_PDPTR_BITS " Lai Jiangshan
2021-11-08 12:43 ` [PATCH 06/15] KVM: X86: Move CR0 pdptr_bits into header file as X86_CR0_PDPTR_BITS Lai Jiangshan
2021-11-08 12:43 ` [PATCH 07/15] KVM: SVM: Remove outdated comment in svm_load_mmu_pgd() Lai Jiangshan
2021-11-08 12:44 ` [PATCH 08/15] KVM: SVM: Remove useless check " Lai Jiangshan
2021-11-08 12:44 ` [PATCH 09/15] KVM: SVM: Remove the unneeded code to mark available for CR3 Lai Jiangshan
2021-11-18 15:17 ` Paolo Bonzini
2021-11-08 12:44 ` [PATCH 10/15] KVM: X86: Mark CR3 dirty when vcpu->arch.cr3 is changed Lai Jiangshan
2021-11-08 12:44 ` [PATCH 11/15] KVM: VMX: Update vmcs.GUEST_CR3 only when the guest CR3 is dirty Lai Jiangshan
2021-12-15 15:47 ` Maxim Levitsky
2021-12-15 16:31 ` Lai Jiangshan
2021-12-15 16:43 ` Lai Jiangshan
2021-12-15 16:45 ` Sean Christopherson
2021-12-15 17:10 ` Paolo Bonzini
2021-12-15 20:21 ` Maxim Levitsky
2021-12-15 20:20 ` Maxim Levitsky
2021-11-08 12:44 ` [PATCH 12/15] KVM: VMX: Reset the bits that are meaningful to be reset in vmx_register_cache_reset() Lai Jiangshan
2021-11-18 15:25 ` Paolo Bonzini
2021-11-08 12:44 ` Lai Jiangshan [this message]
2021-11-18 15:37 ` [PATCH 13/15] KVM: SVM: Add and use svm_register_cache_reset() Paolo Bonzini
2021-11-18 16:28 ` Lai Jiangshan
2021-11-18 17:54 ` Paolo Bonzini
2021-11-19 0:49 ` Lai Jiangshan
2021-11-08 12:44 ` [PATCH 14/15] KVM: X86: Remove kvm_register_clear_available() Lai Jiangshan
2021-11-08 12:44 ` [PATCH 15/15] KVM: nVMX: Always write vmcs.GUEST_CR3 during nested VM-Exit Lai Jiangshan
2021-11-18 15:52 ` Paolo Bonzini
2021-11-11 14:45 ` [PATCH 16/15] KVM: X86: Update mmu->pdptrs only when it is changed Lai Jiangshan
2021-12-07 23:43 ` Sean Christopherson
2021-12-08 3:29 ` Lai Jiangshan
2021-12-08 9:09 ` Paolo Bonzini
2021-12-08 9:34 ` Lai Jiangshan
2021-11-11 14:46 ` [PATCH 17/15] KVM: X86: Ensure pae_root to be reconstructed for shadow paging if the guest PDPTEs " Lai Jiangshan
2021-11-23 9:34 ` Lai Jiangshan
2021-12-08 0:15 ` Sean Christopherson
2021-12-08 4:00 ` Lai Jiangshan
2021-12-08 15:29 ` Sean Christopherson
2021-12-09 22:46 ` Paolo Bonzini
2021-12-10 21:07 ` Sean Christopherson
2021-12-10 21:08 ` Sean Christopherson
2021-12-11 6:56 ` Maxim Levitsky
2021-12-11 8:22 ` Paolo Bonzini
2021-12-13 16:54 ` Sean Christopherson
2021-11-18 8:53 ` [PATCH 00/15] KVM: X86: Fix and clean up for register caches Lai Jiangshan
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