From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2646C43217 for ; Tue, 14 Dec 2021 17:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236463AbhLNR2X (ORCPT ); Tue, 14 Dec 2021 12:28:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236335AbhLNR2V (ORCPT ); Tue, 14 Dec 2021 12:28:21 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDFEFC06173F for ; Tue, 14 Dec 2021 09:28:20 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id y125-20020a25dc83000000b005c2326bf744so37239660ybe.21 for ; Tue, 14 Dec 2021 09:28:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=CnCGzCYE1Jp0ccvw5GdrZXd9S5GY17k/2+AkR8b+f3U=; b=JqmnUyDmZv8NDbsX+KT61C1HiK40r92cnQ71J8DegUkBMlbvIGpJMPfyMUzIX2mAMi ykbqhoJBy+Oo4r3Nmn3y/A5XleGTngiMdeti7+tyEjD4bSm3zFFb97VAnPtwhHAwDK3f Vu3YWkyYRlgJL+yRynYQ61lzU/KWvZ9T9r7PZc1tEUA3YU6azONq/QbY0EJe0Ny/qTgb x7x7vFzZeOdCarffSlvZUqkPxpwUx9/Pk0+4J8wtDBAttgKyUAhjqPrNnUCXBQWR+51h vsoQOCtcrXUGe/gS9FITd4EtmIJFWQnVmpq/w0Mp+pSDGNrLOd4e9fAswZv21dQqYtw7 blHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=CnCGzCYE1Jp0ccvw5GdrZXd9S5GY17k/2+AkR8b+f3U=; b=imGCaDdO4lAznfn08F0OWab+i1/3VAvz9PEaZD5hLRL9VSBhrO8yDy2dmeSzIGNxQ7 6JgPU4u7jOiGehJtX8FRXoGfFdVe8CacoOEIdHChCrjFL7Ysq+14zFZVkT+X/NaE27qJ Tv3tsRJqhv5Pz4zT2bWtokfoWvz0sCDgUYThCsr8WYmnnMWlYK3Cs+TV2Yw9HuZiG6Gh jdPI2rxuLG/biNCmpIQgVD+1fAeLSWv2o7YvB4elz+EajYIYX3LRus4Simm2r9o3Fik9 z10etS9bnYt+rc8Dzqo2sq4WFp0OWHe9d6FpfFSc+GiM3Xq5gQWcS72c3WUUEGgKtkPe YSJQ== X-Gm-Message-State: AOAM530xxcy6uYoyC59SAebFHuJKILNHeQ8SvpVSSfddk4uz23R/SbE+ VU/5+ZHPybVIEMA0q8Ajo9blvTZ4Hms= X-Google-Smtp-Source: ABdhPJzAsUEylnvZJCE0SInf4OnMrGWQsjC+orgNExLoeP/ikgqZwPBpXbNkG6p75hxZJfaLJ7xLmhDMFc0= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a5b:ecc:: with SMTP id a12mr345048ybs.347.1639502900086; Tue, 14 Dec 2021 09:28:20 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:09 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-4-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 3/6] KVM: arm64: Allow guest to set the OSLK bit From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allow writes to OSLAR and forward the OSLK bit to OSLSR. Do nothing with the value for now. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/include/asm/sysreg.h | 9 ++++++++ arch/arm64/kvm/sys_regs.c | 39 ++++++++++++++++++++++++++------- 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16b3f1a1d468..46f800bda045 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -129,7 +129,16 @@ #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) + +#define SYS_OSLAR_OSLK BIT(0) + #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) + +#define SYS_OSLSR_OSLK BIT(1) + +#define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0)) +#define SYS_OSLSR_OSLM BIT(3) + #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7bf350b3d9cd..5188a74095e3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -44,6 +44,10 @@ * 64bit interface. */ +static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); +static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); +static u64 sys_reg_to_index(const struct sys_reg_desc *reg); + static bool read_from_write_only(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r) @@ -287,6 +291,24 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, return trap_raz_wi(vcpu, p, r); } +static bool trap_oslar_el1(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + u64 oslsr; + + if (!p->is_write) + return read_from_write_only(vcpu, p, r); + + /* Forward the OSLK bit to OSLSR */ + oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; + if (p->regval & SYS_OSLAR_OSLK) + oslsr |= SYS_OSLSR_OSLK; + + __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; + return true; +} + static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -309,9 +331,14 @@ static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, if (err) return err; - if (val != rd->val) + /* + * The only modifiable bit is the OSLK bit. Refuse the write if + * userspace attempts to change any other bit in the register. + */ + if ((val & ~SYS_OSLSR_OSLK) != SYS_OSLSR_OSLM) return -EINVAL; + __vcpu_sys_reg(vcpu, rd->reg) = val; return 0; } @@ -1180,10 +1207,6 @@ static bool access_raz_id_reg(struct kvm_vcpu *vcpu, return __access_id_reg(vcpu, p, r, true); } -static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); -static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); -static u64 sys_reg_to_index(const struct sys_reg_desc *reg); - /* Visibility overrides for SVE-specific control registers */ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -1463,8 +1486,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { DBG_BCR_BVR_WCR_WVR_EL1(15), { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008, + { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, SYS_OSLSR_OSLM, .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, @@ -1937,7 +1960,7 @@ static const struct sys_reg_desc cp14_regs[] = { DBGBXVR(0), /* DBGOSLAR */ - { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, + { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, DBGBXVR(1), /* DBGOSLSR */ { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, -- 2.34.1.173.g76aa8bc2d0-goog