From: Oliver Upton <oupton@google.com>
To: kvm@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Oliver Upton <oupton@google.com>
Subject: [PATCH v2 6/7] selftests: KVM: Add test for BNDCFGS VMX control MSR bits
Date: Fri, 4 Feb 2022 20:47:04 +0000 [thread overview]
Message-ID: <20220204204705.3538240-7-oupton@google.com> (raw)
In-Reply-To: <20220204204705.3538240-1-oupton@google.com>
Test that the default behavior of KVM is to ignore userspace MSR writes
and conditionally expose the "{load,clear} IA32_BNDCFGS" bits in the VMX
control MSRs if the guest CPUID exposes MPX. Additionally, test that
when the corresponding quirk is disabled, userspace can still clear
these bits regardless of what is exposed in CPUID.
Signed-off-by: Oliver Upton <oupton@google.com>
---
.../selftests/kvm/include/x86_64/vmx.h | 2 +
.../kvm/x86_64/vmx_control_msrs_test.c | 53 +++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/x86_64/vmx.h b/tools/testing/selftests/kvm/include/x86_64/vmx.h
index 583ceb0d1457..811c66d9be74 100644
--- a/tools/testing/selftests/kvm/include/x86_64/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86_64/vmx.h
@@ -80,6 +80,7 @@
#define VM_EXIT_SAVE_IA32_EFER 0x00100000
#define VM_EXIT_LOAD_IA32_EFER 0x00200000
#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
+#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
@@ -90,6 +91,7 @@
#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
+#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
diff --git a/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c
index ac5fdeb50eee..21e1dee0f83f 100644
--- a/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c
@@ -96,6 +96,58 @@ static void load_perf_global_ctrl_test(struct kvm_vm *vm)
VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
0,
VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
+
+ /* cleanup, enable the quirk again */
+ cap.args[0] = 0;
+ vm_enable_cap(vm, &cap);
+}
+
+static void bndcfgs_test(struct kvm_vm *vm)
+{
+ uint32_t entry_low, entry_high, exit_low, exit_high;
+ struct kvm_enable_cap cap = {0};
+
+ get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, &entry_low, &entry_high);
+ get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, &exit_low, &exit_high);
+
+ if (!(entry_high & VM_ENTRY_LOAD_BNDCFGS) ||
+ !(exit_high & VM_EXIT_CLEAR_BNDCFGS)) {
+ print_skip("\"load/clear IA32_BNDCFGS\" VM-{Entry,Exit} controls not supported");
+ return;
+ }
+
+ /*
+ * Test that KVM will set these bits regardless of userspace if the
+ * guest CPUID exposes MPX.
+ */
+ test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, 0,
+ VM_ENTRY_LOAD_BNDCFGS,
+ VM_ENTRY_LOAD_BNDCFGS,
+ 0);
+ test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, 0,
+ VM_EXIT_CLEAR_BNDCFGS,
+ VM_EXIT_CLEAR_BNDCFGS,
+ 0);
+
+ /*
+ * Disable the quirk, giving userspace control of the VMX capability
+ * MSRs.
+ */
+ cap.cap = KVM_CAP_DISABLE_QUIRKS;
+ cap.args[0] = KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS;
+ vm_enable_cap(vm, &cap);
+
+ /*
+ * Test that userspace can clear these bits, even if it exposes MPX.
+ */
+ test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, 0,
+ VM_ENTRY_LOAD_BNDCFGS,
+ 0,
+ VM_ENTRY_LOAD_BNDCFGS);
+ test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, 0,
+ VM_EXIT_CLEAR_BNDCFGS,
+ 0,
+ VM_EXIT_CLEAR_BNDCFGS);
}
int main(void)
@@ -108,6 +160,7 @@ int main(void)
vm = vm_create_default(VCPU_ID, 0, NULL);
load_perf_global_ctrl_test(vm);
+ bndcfgs_test(vm);
kvm_vm_free(vm);
}
--
2.35.0.263.gb82422642f-goog
next prev parent reply other threads:[~2022-02-04 20:47 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-04 20:46 [PATCH v2 0/7] VMX: nVMX: VMX control MSR fixes Oliver Upton
2022-02-04 20:46 ` [PATCH v2 1/7] KVM: nVMX: Keep KVM updates to BNDCFGS ctrl bits across MSR write Oliver Upton
2022-02-07 17:21 ` Paolo Bonzini
2022-02-07 18:13 ` Sean Christopherson
2022-02-07 18:22 ` Oliver Upton
2022-02-07 18:27 ` Paolo Bonzini
2022-02-07 18:34 ` Sean Christopherson
2022-02-07 18:52 ` Oliver Upton
2022-02-04 20:47 ` [PATCH v2 2/7] KVM: nVMX: Keep KVM updates to PERF_GLOBAL_CTRL " Oliver Upton
2022-02-07 16:33 ` Paolo Bonzini
2022-02-04 20:47 ` [PATCH v2 3/7] KVM: nVMX: Roll all entry/exit ctl updates into a single helper Oliver Upton
2022-02-05 7:43 ` kernel test robot
2022-02-05 19:41 ` Oliver Upton
2022-02-07 17:56 ` Sean Christopherson
2022-02-04 20:47 ` [PATCH v2 4/7] KVM: nVMX: Add a quirk for KVM tweaks to VMX control MSRs Oliver Upton
2022-02-07 18:06 ` Sean Christopherson
2022-02-09 1:50 ` Oliver Upton
2022-02-09 20:23 ` Sean Christopherson
2022-02-04 20:47 ` [PATCH v2 5/7] selftests: KVM: Add test for PERF_GLOBAL_CTRL VMX control MSR bits Oliver Upton
2022-02-04 20:47 ` Oliver Upton [this message]
2022-02-07 16:42 ` [PATCH v2 6/7] selftests: KVM: Add test for BNDCFGS " Paolo Bonzini
2022-02-04 20:47 ` [PATCH v2 7/7] KVM: VMX: Use local pointer to vcpu_vmx in vmx_vcpu_after_set_cpuid() Oliver Upton
2022-02-07 16:42 ` Paolo Bonzini
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