From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
Fuad Tabba <tabba@google.com>,
Peng Liang <liangpeng10@huawei.com>,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Jing Zhang <jingzhangos@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [PATCH v5 02/27] KVM: arm64: Save ID registers' sanitized value per guest
Date: Sun, 13 Feb 2022 22:57:21 -0800 [thread overview]
Message-ID: <20220214065746.1230608-3-reijiw@google.com> (raw)
In-Reply-To: <20220214065746.1230608-1-reijiw@google.com>
Introduce id_regs[] in kvm_arch as a storage of guest's ID registers,
and save ID registers' sanitized value in the array at KVM_CREATE_VM.
Use the saved ones when ID registers are read by the guest or
userspace (via KVM_GET_ONE_REG).
Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
arch/arm64/include/asm/kvm_host.h | 12 ++++++
arch/arm64/kvm/arm.c | 1 +
arch/arm64/kvm/sys_regs.c | 65 ++++++++++++++++++++++++-------
3 files changed, 63 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 2869259e10c0..c041e5afe3d2 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -101,6 +101,13 @@ struct kvm_s2_mmu {
struct kvm_arch_memory_slot {
};
+/*
+ * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2),
+ * where 0<=crm<8, 0<=op2<8.
+ */
+#define KVM_ARM_ID_REG_MAX_NUM 64
+#define IDREG_IDX(id) ((sys_reg_CRm(id) << 3) | sys_reg_Op2(id))
+
struct kvm_arch {
struct kvm_s2_mmu mmu;
@@ -137,6 +144,9 @@ struct kvm_arch {
/* Memory Tagging Extension enabled for the guest */
bool mte_enabled;
bool ran_once;
+
+ /* ID registers for the guest. */
+ u64 id_regs[KVM_ARM_ID_REG_MAX_NUM];
};
struct kvm_vcpu_fault_info {
@@ -736,6 +746,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
struct kvm_arm_copy_mte_tags *copy_tags);
+void set_default_id_regs(struct kvm *kvm);
+
/* Guest/host FPSIMD coordination helpers */
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 4783dbf66df2..91110d996ed6 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -156,6 +156,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
kvm->arch.max_vcpus = kvm_arm_default_max_vcpus();
set_default_spectre(kvm);
+ set_default_id_regs(kvm);
return ret;
out_free_stage2_pgd:
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 4dc2fba316ff..080908c60fa6 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -33,6 +33,8 @@
#include "trace.h"
+static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
+
/*
* All of this file is extremely similar to the ARM coproc.c, but the
* types are different. My gut feeling is that it should be pretty
@@ -273,7 +275,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
+ u64 val = __read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
u32 sr = reg_to_encoding(r);
if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
@@ -1059,17 +1061,16 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
return true;
}
-/* Read a sanitised cpufeature ID register by sys_reg_desc */
-static u64 read_id_reg(const struct kvm_vcpu *vcpu,
- struct sys_reg_desc const *r, bool raz)
+static bool is_id_reg(u32 id)
{
- u32 id = reg_to_encoding(r);
- u64 val;
-
- if (raz)
- return 0;
+ return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
+ sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 0 &&
+ sys_reg_CRm(id) < 8);
+}
- val = read_sanitised_ftr_reg(id);
+static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
+{
+ u64 val = vcpu->kvm->arch.id_regs[IDREG_IDX(id)];
switch (id) {
case SYS_ID_AA64PFR0_EL1:
@@ -1119,6 +1120,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
return val;
}
+static u64 read_id_reg(const struct kvm_vcpu *vcpu,
+ struct sys_reg_desc const *r, bool raz)
+{
+ u32 id = reg_to_encoding(r);
+
+ return raz ? 0 : __read_id_reg(vcpu, id);
+}
+
static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
@@ -1223,9 +1232,8 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
/*
* cpufeature ID register user accessors
*
- * For now, these registers are immutable for userspace, so no values
- * are stored, and for set_id_reg() we don't allow the effective value
- * to be changed.
+ * For now, these registers are immutable for userspace, so for set_id_reg()
+ * we don't allow the effective value to be changed.
*/
static int __get_id_reg(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd, void __user *uaddr,
@@ -1837,8 +1845,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
if (p->is_write) {
return ignore_write(vcpu, p);
} else {
- u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
- u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
+ u64 dfr = __read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
+ u64 pfr = __read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
@@ -2850,3 +2858,30 @@ void kvm_sys_reg_table_init(void)
/* Clear all higher bits. */
cache_levels &= (1 << (i*3))-1;
}
+
+/*
+ * Set the guest's ID registers that are defined in sys_reg_descs[]
+ * with ID_SANITISED() to the host's sanitized value.
+ */
+void set_default_id_regs(struct kvm *kvm)
+{
+ int i;
+ u32 id;
+ const struct sys_reg_desc *rd;
+ u64 val;
+
+ for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
+ rd = &sys_reg_descs[i];
+ if (rd->access != access_id_reg)
+ /* Not ID register, or hidden/reserved ID register */
+ continue;
+
+ id = reg_to_encoding(rd);
+ if (WARN_ON_ONCE(!is_id_reg(id)))
+ /* Shouldn't happen */
+ continue;
+
+ val = read_sanitised_ftr_reg(id);
+ kvm->arch.id_regs[IDREG_IDX(id)] = val;
+ }
+}
--
2.35.1.265.g69c8d7142f-goog
next prev parent reply other threads:[~2022-02-14 6:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 6:57 [PATCH v5 00/27] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 01/27] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2022-02-14 6:57 ` Reiji Watanabe [this message]
2022-02-14 6:57 ` [PATCH v5 03/27] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2022-02-17 5:14 ` Oliver Upton
2022-02-22 6:12 ` Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 04/27] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 05/27] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 06/27] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 07/27] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 08/27] KVM: arm64: Make ID_AA64MMFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 09/27] KVM: arm64: Make ID_AA64MMFR1_EL1 writable Reiji Watanabe
2022-02-15 18:53 ` Oliver Upton
2022-02-15 20:24 ` Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 10/27] KVM: arm64: Hide IMPLEMENTATION DEFINED PMU support for the guest Reiji Watanabe
2022-02-15 18:57 ` Oliver Upton
2022-02-16 2:52 ` Reiji Watanabe
2022-02-17 4:59 ` Oliver Upton
2022-02-14 6:57 ` [PATCH v5 11/27] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 12/27] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 13/27] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 14/27] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 15/27] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 16/27] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_CONFIGURABLE capability Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 17/27] KVM: arm64: Add kunit test for ID register validation Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 18/27] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 19/27] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 20/27] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 21/27] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 22/27] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 23/27] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 24/27] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 25/27] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 26/27] KVM: arm64: Add kunit test for trap initialization Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 27/27] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
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