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From: Jue Wang <juew@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
	David Matlack <dmatlack@google.com>
Cc: Tony Luck <tony.luck@intel.com>,
	kvm@vger.kernel.org, Greg Thelen <gthelen@google.com>,
	Jiaqi Yan <jiaqiyan@google.com>, Jue Wang <juew@google.com>
Subject: [PATCH v4 3/8] KVM: x86: Add APIC_LVTx() macro.
Date: Fri, 20 May 2022 10:36:33 -0700	[thread overview]
Message-ID: <20220520173638.94324-4-juew@google.com> (raw)
In-Reply-To: <20220520173638.94324-1-juew@google.com>

To implement Corrected Machine Check Interrupt (CMCI) as an additional
LVT vector, the code needs to be able to calculate the APIC_LVTx register
offset based on the register indices in the lapic_lvt_entry enum which
will be used in all places looping through supported APIC_LVTx
registers.

APIC_LVTx macro is introduced for this purpose.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Jue Wang <juew@google.com>
---
 arch/x86/kvm/lapic.c | 7 +++----
 arch/x86/kvm/lapic.h | 2 ++
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 73f5cd248a63..db12d2ef1aef 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2086,9 +2086,8 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 			u32 lvt_val;
 
 			for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++) {
-				lvt_val = kvm_lapic_get_reg(apic,
-						       APIC_LVTT + 0x10 * i);
-				kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
+				lvt_val = kvm_lapic_get_reg(apic, APIC_LVTx(i));
+				kvm_lapic_set_reg(apic, APIC_LVTx(i),
 					     lvt_val | APIC_LVT_MASKED);
 			}
 			apic_update_lvtt(apic);
@@ -2385,7 +2384,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
 	kvm_apic_set_version(apic->vcpu);
 
 	for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++)
-		kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
+		kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);
 	apic_update_lvtt(apic);
 	if (kvm_vcpu_is_reset_bsp(vcpu) &&
 	    kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 4990793c2034..2d197ed0b8ce 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -39,6 +39,8 @@ enum lapic_lvt_entry {
 	KVM_APIC_MAX_NR_LVT_ENTRIES,
 };
 
+#define APIC_LVTx(x) (APIC_LVTT + 0x10 * (x))
+
 struct kvm_timer {
 	struct hrtimer timer;
 	s64 period; 				/* unit: ns */
-- 
2.36.1.124.g0e6072fb45-goog


  parent reply	other threads:[~2022-05-20 17:36 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 17:36 [PATCH v4 0/8] KVM: x86: Add CMCI and UCNA emulation Jue Wang
2022-05-20 17:36 ` [PATCH v4 1/8] KVM: x86: Make APIC_VERSION capture only the magic 0x14UL Jue Wang
2022-06-03 18:58   ` David Matlack
2022-06-03 20:28     ` David Matlack
2022-05-20 17:36 ` [PATCH v4 2/8] KVM: x86: Fill apic_lvt_mask with enums / explicit entries Jue Wang
2022-05-20 17:36 ` Jue Wang [this message]
2022-05-20 17:36 ` [PATCH v4 4/8] KVM: x86: Add Corrected Machine Check Interrupt (CMCI) emulation to lapic Jue Wang
2022-06-03 20:26   ` David Matlack
2022-05-20 17:36 ` [PATCH v4 5/8] KVM: x86: Use kcalloc to allocate the mce_banks array Jue Wang
2022-05-20 17:36 ` [PATCH v4 6/8] KVM: x86: Add emulation for MSR_IA32_MCx_CTL2 MSRs Jue Wang
2022-06-03 20:41   ` David Matlack
2022-05-20 17:36 ` [PATCH v4 7/8] KVM: x86: Enable CMCI capability by default and handle injected UCNA errors Jue Wang
2022-06-03 20:54   ` David Matlack
2022-05-20 17:36 ` [RFC v4 8/8] KVM: selftests: Add a self test for UCNA injection Jue Wang
2022-05-20 21:08   ` David Matlack
2022-05-20 22:16     ` Jue Wang

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