From: Robert Hoo <robert.hu@linux.intel.com>
To: seanjc@google.com, pbonzini@redhat.com
Cc: kvm@vger.kernel.org, Robert Hoo <robert.hu@linux.intel.com>
Subject: [PATCH 1/9] KVM: x86: Rename cr4_reserved/rsvd_* variables to be more readable
Date: Mon, 17 Oct 2022 15:04:42 +0800 [thread overview]
Message-ID: <20221017070450.23031-2-robert.hu@linux.intel.com> (raw)
In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com>
kvm_vcpu_arch::cr4_guest_owned_bits and kvm_vcpu_arch::cr4_guest_rsvd_bits
looks confusing. Rename latter to cr4_host_rsvd_bits, because it in fact
decribes the effective host reserved cr4 bits from the vcpu's perspective.
Meanwhile, rename other related variables/macros to be better descriptive:
* CR4_RESERVED_BITS --> CR4_HOST_RESERVED_BITS, which describes host bare
metal CR4 reserved bits.
* cr4_reserved_bits --> cr4_kvm_reserved_bits, which describes
CR4_HOST_RESERVED_BITS + !kvm_cap_has() = kvm level cr4 reserved bits.
* __cr4_reserved_bits() --> __cr4_calc_reserved_bits(), which to calc
effective cr4 reserved bits for kvm or vm level, by corresponding
x_cpu_has() input.
Thus, by these renames, the hierarchical relations of those reserved CR4
bits is more clear.
Just renames, no functional changes intended.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
---
arch/x86/include/asm/kvm_host.h | 4 ++--
arch/x86/kvm/cpuid.c | 4 ++--
arch/x86/kvm/vmx/vmx.c | 2 +-
arch/x86/kvm/x86.c | 12 ++++++------
arch/x86/kvm/x86.h | 4 ++--
5 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 5ffa578cafe1..4858436c64ef 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -114,7 +114,7 @@
| X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
| X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
-#define CR4_RESERVED_BITS \
+#define CR4_HOST_RESERVED_BITS \
(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
| X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
@@ -654,7 +654,7 @@ struct kvm_vcpu_arch {
unsigned long cr3;
unsigned long cr4;
unsigned long cr4_guest_owned_bits;
- unsigned long cr4_guest_rsvd_bits;
+ unsigned long cr4_host_rsvd_bits;
unsigned long cr8;
u32 host_pkru;
u32 pkru;
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 75dcf7a72605..b935b3b04a7e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -338,8 +338,8 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
kvm_pmu_refresh(vcpu);
- vcpu->arch.cr4_guest_rsvd_bits =
- __cr4_reserved_bits(guest_cpuid_has, vcpu);
+ vcpu->arch.cr4_host_rsvd_bits =
+ __cr4_calc_reserved_bits(guest_cpuid_has, vcpu);
kvm_hv_set_cpuid(vcpu);
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index d7f8331d6f7e..97a2b8759ce8 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -4294,7 +4294,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
struct kvm_vcpu *vcpu = &vmx->vcpu;
vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
- ~vcpu->arch.cr4_guest_rsvd_bits;
+ ~vcpu->arch.cr4_host_rsvd_bits;
if (!enable_ept) {
vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS;
vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 205ebdc2b11b..05a40ab7cda2 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -108,7 +108,7 @@ u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
#endif
-static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
+static u64 __read_mostly cr4_kvm_reserved_bits = CR4_HOST_RESERVED_BITS;
#define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
@@ -1082,10 +1082,10 @@ EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
{
- if (cr4 & cr4_reserved_bits)
+ if (cr4 & cr4_kvm_reserved_bits)
return false;
- if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
+ if (cr4 & vcpu->arch.cr4_host_rsvd_bits)
return false;
return true;
@@ -11965,7 +11965,7 @@ int kvm_arch_hardware_setup(void *opaque)
kvm_caps.supported_xss = 0;
#define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
- cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
+ cr4_kvm_reserved_bits = __cr4_calc_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
#undef __kvm_cpu_cap_has
if (kvm_caps.has_tsc_control) {
@@ -11998,8 +11998,8 @@ int kvm_arch_check_processor_compat(void *opaque)
WARN_ON(!irqs_disabled());
- if (__cr4_reserved_bits(cpu_has, c) !=
- __cr4_reserved_bits(cpu_has, &boot_cpu_data))
+ if (__cr4_calc_reserved_bits(cpu_has, c) !=
+ __cr4_calc_reserved_bits(cpu_has, &boot_cpu_data))
return -EIO;
return ops->check_processor_compatibility();
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 1926d2cb8e79..4473bc0ba0f1 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -448,9 +448,9 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
#define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
#define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
-#define __cr4_reserved_bits(__cpu_has, __c) \
+#define __cr4_calc_reserved_bits(__cpu_has, __c) \
({ \
- u64 __reserved_bits = CR4_RESERVED_BITS; \
+ u64 __reserved_bits = CR4_HOST_RESERVED_BITS; \
\
if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
__reserved_bits |= X86_CR4_OSXSAVE; \
--
2.31.1
next prev parent reply other threads:[~2022-10-17 7:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-17 7:04 [PATCH 0/9] Linear Address Masking (LAM) KVM Enabling Robert Hoo
2022-10-17 7:04 ` Robert Hoo [this message]
2022-10-17 7:04 ` [PATCH 2/9] KVM: x86: Add CR4.LAM_SUP in guest owned bits Robert Hoo
2022-10-17 7:04 ` [PATCH 3/9] KVM: x86: MMU: Rename get_cr3() --> get_pgd() and clear high bits for pgd Robert Hoo
2022-10-17 7:04 ` [PATCH 4/9] [Trivial] KVM: x86: MMU: Commets update Robert Hoo
2022-10-17 7:04 ` [PATCH 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3 Robert Hoo
2022-10-17 7:04 ` [PATCH 6/9] KVM: x86: Untag LAM bits when applicable Robert Hoo
2022-10-17 7:04 ` [PATCH 7/9] KVM: x86: When judging setting CR3 valid or not, consider LAM bits Robert Hoo
2022-10-17 7:04 ` [PATCH 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics Robert Hoo
2022-10-31 2:59 ` Kirill A. Shutemov
2022-11-01 1:46 ` Robert Hoo
2022-11-01 2:04 ` Kirill A. Shutemov
2022-11-01 2:26 ` Robert Hoo
2022-11-02 7:29 ` Robert Hoo
2022-11-02 21:05 ` Kirill A. Shutemov
2022-11-03 1:04 ` Robert Hoo
2022-11-03 2:40 ` Kirill A. Shutemov
2022-11-03 8:07 ` Robert Hoo
2022-10-17 7:04 ` [PATCH 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM Robert Hoo
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