[PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[Babu Moger]

This series adds following changes.
a. Allow versioned CPUs to specify new cache_info pointers.
b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
   cache_info.complex_indexing.
c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
---
v2:
  Refreshed the patches on top of latest master.
  Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE to
  match the kernel name.
  https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phillips@amd.com/

v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/


Babu Moger (3):
  target/i386: Add a couple of feature bits in 8000_0008_EBX
  target/i386: Add feature bits for CPUID_Fn80000021_EAX
  target/i386: Add missing feature bits in EPYC-Milan model

Michael Roth (2):
  target/i386: allow versioned CPUs to specify new cache_info
  target/i386: Add new EPYC CPU versions with updated cache_info

 target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++-
 target/i386/cpu.h |  12 +++
 2 files changed, 259 insertions(+), 5 deletions(-)

-- 
2.34.1

[PATCH v2 1/5] target/i386: allow versioned CPUs to specify new cache_info

[Babu Moger]

From: Michael Roth <michael.roth@amd.com>

New EPYC CPUs versions require small changes to their cache_info's.
Because current QEMU x86 CPU definition does not support cache
versions, we would have to declare a new CPU type for each such case.
To avoid this duplication, the patch allows new cache_info pointers
to be specified for a new CPU version.

Co-developed-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3410e5e470..ab1b49f08f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1596,6 +1596,7 @@ typedef struct X86CPUVersionDefinition {
     const char *alias;
     const char *note;
     PropValue *props;
+    const CPUCaches *const cache_info;
 } X86CPUVersionDefinition;
 
 /* Base definition for a CPU model */
@@ -5057,6 +5058,32 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
     assert(vdef->version == version);
 }
 
+/* Apply properties for the CPU model version specified in model */
+static const CPUCaches *x86_cpu_get_version_cache_info(X86CPU *cpu,
+                                                       X86CPUModel *model)
+{
+    const X86CPUVersionDefinition *vdef;
+    X86CPUVersion version = x86_cpu_model_resolve_version(model);
+    const CPUCaches *cache_info = model->cpudef->cache_info;
+
+    if (version == CPU_VERSION_LEGACY) {
+        return cache_info;
+    }
+
+    for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
+        if (vdef->cache_info) {
+            cache_info = vdef->cache_info;
+        }
+
+        if (vdef->version == version) {
+            break;
+        }
+    }
+
+    assert(vdef->version == version);
+    return cache_info;
+}
+
 /*
  * Load data from X86CPUDefinition into a X86CPU object.
  * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
@@ -5089,7 +5116,7 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
     }
 
     /* legacy-cache defaults to 'off' if CPU model provides cache info */
-    cpu->legacy_cache = !def->cache_info;
+    cpu->legacy_cache = !x86_cpu_get_version_cache_info(cpu, model);
 
     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
 
@@ -6563,14 +6590,17 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
 
     /* Cache information initialization */
     if (!cpu->legacy_cache) {
-        if (!xcc->model || !xcc->model->cpudef->cache_info) {
+        const CPUCaches *cache_info =
+            x86_cpu_get_version_cache_info(cpu, xcc->model);
+
+        if (!xcc->model || !cache_info) {
             g_autofree char *name = x86_cpu_class_get_model_name(xcc);
             error_setg(errp,
                        "CPU model '%s' doesn't support legacy-cache=off", name);
             return;
         }
         env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
-            *xcc->model->cpudef->cache_info;
+            *cache_info;
     } else {
         /* Build legacy cache information */
         env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
-- 
2.34.1

[PATCH v2 2/5] target/i386: Add new EPYC CPU versions with updated cache_info

[Babu Moger]

From: Michael Roth <michael.roth@amd.com>

Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
The only difference vs. older models is an updated cache_info with
the 'complex_indexing' bit unset, since this bit is not currently
defined for AMD and may cause problems should it be used for
something else in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.

Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ab1b49f08f..2dffd12081 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1705,6 +1705,56 @@ static const CPUCaches epyc_cache_info = {
     },
 };
 
+static CPUCaches epyc_v4_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 64 * KiB,
+        .line_size = 64,
+        .associativity = 4,
+        .partitions = 1,
+        .sets = 256,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 8 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 8192,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = false,
+    },
+};
+
 static const CPUCaches epyc_rome_cache_info = {
     .l1d_cache = &(CPUCacheInfo) {
         .type = DATA_CACHE,
@@ -1755,6 +1805,56 @@ static const CPUCaches epyc_rome_cache_info = {
     },
 };
 
+static const CPUCaches epyc_rome_v3_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 16 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 16384,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = false,
+    },
+};
+
 static const CPUCaches epyc_milan_cache_info = {
     .l1d_cache = &(CPUCacheInfo) {
         .type = DATA_CACHE,
@@ -3960,6 +4060,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 4,
+                .props = (PropValue[]) {
+                    { "model-id",
+                      "AMD EPYC-v4 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_v4_cache_info
+            },
             { /* end of list */ }
         }
     },
@@ -4079,6 +4188,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "model-id",
+                      "AMD EPYC-Rome-v3 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_rome_v3_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.34.1

[PATCH v2 3/5] target/i386: Add a couple of feature bits in 8000_0008_EBX

[Babu Moger]

Add the following feature bits.

amd-psfd : Predictive Store Forwarding Disable:
           PSF is a hardware-based micro-architectural optimization
           designed to improve the performance of code execution by
           predicting address dependencies between loads and stores.
           While SSBD (Speculative Store Bypass Disable) disables both
           PSF and speculative store bypass, PSFD only disables PSF.
           PSFD may be desirable for the software which is concerned
           with the speculative behavior of PSF but desires a smaller
           performance impact than setting SSBD.
	   Depends on the following kernel commit:
           b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable")

stibp-always-on :
           Single Thread Indirect Branch Prediction mode has enhanced
           performance and may be left always on.

The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
   Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING

Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c | 4 ++--
 target/i386/cpu.h | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2dffd12081..117130fba1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -909,10 +909,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             NULL, NULL, NULL, NULL,
             NULL, "wbnoinvd", NULL, NULL,
             "ibpb", NULL, "ibrs", "amd-stibp",
-            NULL, NULL, NULL, NULL,
+            NULL, "stibp-always-on", NULL, NULL,
             NULL, NULL, NULL, NULL,
             "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
-            NULL, NULL, NULL, NULL,
+            "amd-psfd", NULL, NULL, NULL,
         },
         .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
         .tcg_features = 0,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d4bc19577a..8c65c92131 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -918,8 +918,12 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define CPUID_8000_0008_EBX_IBRS        (1U << 14)
 /* Single Thread Indirect Branch Predictors */
 #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
+/* STIBP mode has enhanced performance and may be left always on */
+#define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON    (1U << 17)
 /* Speculative Store Bypass Disable */
 #define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
+/* Predictive Store Forwarding Disable */
+#define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
 
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)
-- 
2.34.1

[PATCH v2 4/5] target/i386: Add feature bits for CPUID_Fn80000021_EAX

[Babu Moger]

Add the following feature bits.
no-nested-data-bp	  : Processor ignores nested data breakpoints.
lfence-always-serializing : LFENCE instruction is always serializing.
null-sel-cls-base	  : Null Selector Clears Base. When this bit is
			    set, a null segment load clears the segment base.

The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
   Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
    40332 4.05 Date October 2022

Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c | 24 ++++++++++++++++++++++++
 target/i386/cpu.h |  8 ++++++++
 2 files changed, 32 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 117130fba1..63c4675569 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -918,6 +918,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .tcg_features = 0,
         .unmigratable_flags = 0,
     },
+    [FEAT_8000_0021_EAX] = {
+        .type = CPUID_FEATURE_WORD,
+        .feat_names = {
+            "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
+            NULL, NULL, "null-sel-clr-base", NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+        },
+        .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
+        .tcg_features = 0,
+        .unmigratable_flags = 0,
+    },
     [FEAT_XSAVE] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
@@ -6001,6 +6017,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             *ebx |= sev_get_reduced_phys_bits() << 6;
         }
         break;
+    case 0x80000021:
+        *eax = env->features[FEAT_8000_0021_EAX];
+        *ebx = *ecx = *edx = 0;
+        break;
     default:
         /* reserved values: zero */
         *eax = 0;
@@ -6430,6 +6450,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
         }
 
+        if (env->features[FEAT_8000_0021_EAX]) {
+            x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
+        }
+
         /* SGX requires CPUID[0x12] for EPC enumeration */
         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
             x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8c65c92131..519dcdc23d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -597,6 +597,7 @@ typedef enum FeatureWord {
     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
     FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
     FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
+    FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
     FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
@@ -925,6 +926,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 /* Predictive Store Forwarding Disable */
 #define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
 
+/* Processor ignores nested data breakpoints */
+#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP    (1U << 0)
+/* LFENCE is always serializing */
+#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
+/* Null Selector Clears Base */
+#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE    (1U << 6)
+
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)
 #define CPUID_XSAVE_XGETBV1    (1U << 2)
-- 
2.34.1

[PATCH v2 5/5] target/i386: Add missing feature bits in EPYC-Milan model

[Babu Moger]

And the following feature bits for EPYC-Milan model and bump the version.
vaes            : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq	: Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
                  performance and may be left Always on
amd-psfd	: Predictive Store Forward Disable
no-nested-data-bp         : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base         : Null Selector Clears Base. When this bit is
                            set, a null segment load clears the segment base

These new features will be added in EPYC-Milan-v2. The -cpu help output
after the change.

    x86 EPYC-Milan             (alias configured by machine type)
    x86 EPYC-Milan-v1          AMD EPYC-Milan Processor
    x86 EPYC-Milan-v2          AMD EPYC-Milan Processor

The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
   Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
    40332 4.05 Date October 2022

Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63c4675569..c2bb11b82a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1921,6 +1921,56 @@ static const CPUCaches epyc_milan_cache_info = {
     },
 };
 
+static const CPUCaches epyc_milan_v2_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 32 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 32768,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = false,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
@@ -4270,6 +4320,26 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC-Milan Processor",
         .cache_info = &epyc_milan_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "model-id",
+                      "AMD EPYC-Milan-v2 Processor" },
+                    { "vaes", "on" },
+                    { "vpclmulqdq", "on" },
+                    { "stibp-always-on", "on" },
+                    { "amd-psfd", "on" },
+                    { "no-nested-data-bp", "on" },
+                    { "lfence-always-serializing", "on" },
+                    { "null-sel-clr-base", "on" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_milan_v2_cache_info
+            },
+            { /* end of list */ }
+        }
     },
 };
 
-- 
2.34.1

Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[Michael S. Tsirkin]

On Fri, Jan 06, 2023 at 12:56:55PM -0600, Babu Moger wrote:
> This series adds following changes.
> a. Allow versioned CPUs to specify new cache_info pointers.
> b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
>    cache_info.complex_indexing.
> c. Introduce EPYC-Milan-v2 by adding few missing feature bits.

Acked-by: Michael S. Tsirkin <mst@redhat.com>

who's merging this btw?
target/i386/cpu.c doesn't have an official maintainer in MAINTAINERS ...

> ---
> v2:
>   Refreshed the patches on top of latest master.
>   Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE to
>   match the kernel name.
>   https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phillips@amd.com/
> 
> v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/
> 
> 
> Babu Moger (3):
>   target/i386: Add a couple of feature bits in 8000_0008_EBX
>   target/i386: Add feature bits for CPUID_Fn80000021_EAX
>   target/i386: Add missing feature bits in EPYC-Milan model
> 
> Michael Roth (2):
>   target/i386: allow versioned CPUs to specify new cache_info
>   target/i386: Add new EPYC CPU versions with updated cache_info
> 
>  target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++-
>  target/i386/cpu.h |  12 +++
>  2 files changed, 259 insertions(+), 5 deletions(-)
> 
> -- 
> 2.34.1

Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[Moger, Babu]

> -----Original Message-----
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Friday, January 27, 2023 6:53 AM
> To: Moger, Babu <Babu.Moger@amd.com>
> Cc: pbonzini@redhat.com; mtosatti@redhat.com; kvm@vger.kernel.org;
> marcel.apfelbaum@gmail.com; imammedo@redhat.com;
> richard.henderson@linaro.org; yang.zhong@intel.com; jing2.liu@intel.com;
> vkuznets@redhat.com; Roth, Michael <Michael.Roth@amd.com>; Huang2, Wei
> <Wei.Huang2@amd.com>
> Subject: Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models
> 
> On Fri, Jan 06, 2023 at 12:56:55PM -0600, Babu Moger wrote:
> > This series adds following changes.
> > a. Allow versioned CPUs to specify new cache_info pointers.
> > b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
> >    cache_info.complex_indexing.
> > c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
> 
> Acked-by: Michael S. Tsirkin <mst@redhat.com>

Michael, Thank you

> 
> who's merging this btw?
> target/i386/cpu.c doesn't have an official maintainer in MAINTAINERS ...

I thought Paolo might pick this up.

Thanks
Babu

> 
> > ---
> > v2:
> >   Refreshed the patches on top of latest master.
> >   Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE
> to
> >   match the kernel name.
> >   https://lore.kernel.org/kvm/20221205233235.622491-3-
> kim.phillips@amd.com/
> >
> > v1:
> https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit
> @bmoger-ubuntu/
> >
> >
> > Babu Moger (3):
> >   target/i386: Add a couple of feature bits in 8000_0008_EBX
> >   target/i386: Add feature bits for CPUID_Fn80000021_EAX
> >   target/i386: Add missing feature bits in EPYC-Milan model
> >
> > Michael Roth (2):
> >   target/i386: allow versioned CPUs to specify new cache_info
> >   target/i386: Add new EPYC CPU versions with updated cache_info
> >
> >  target/i386/cpu.c | 252
> +++++++++++++++++++++++++++++++++++++++++++++-
> >  target/i386/cpu.h |  12 +++
> >  2 files changed, 259 insertions(+), 5 deletions(-)
> >
> > --
> > 2.34.1

Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[Moger, Babu]

Gentle ping again. Hope this patch doesn't get lost.
Thanks
Babu

On 1/31/23 14:21, Moger, Babu wrote:
> 
>> -----Original Message-----
>> From: Michael S. Tsirkin <mst@redhat.com>
>> Sent: Friday, January 27, 2023 6:53 AM
>> To: Moger, Babu <Babu.Moger@amd.com>
>> Cc: pbonzini@redhat.com; mtosatti@redhat.com; kvm@vger.kernel.org;
>> marcel.apfelbaum@gmail.com; imammedo@redhat.com;
>> richard.henderson@linaro.org; yang.zhong@intel.com; jing2.liu@intel.com;
>> vkuznets@redhat.com; Roth, Michael <Michael.Roth@amd.com>; Huang2, Wei
>> <Wei.Huang2@amd.com>
>> Subject: Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models
>>
>> On Fri, Jan 06, 2023 at 12:56:55PM -0600, Babu Moger wrote:
>> > This series adds following changes.
>> > a. Allow versioned CPUs to specify new cache_info pointers.
>> > b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
>> >    cache_info.complex_indexing.
>> > c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
>>
>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> 
> Michael, Thank you
> 
>>
>> who's merging this btw?
>> target/i386/cpu.c doesn't have an official maintainer in MAINTAINERS ...
> 
> I thought Paolo might pick this up.
> 
> Thanks
> Babu
> 
>>
>> > ---
>> > v2:
>> >   Refreshed the patches on top of latest master.
>> >   Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE
>> to
>> >   match the kernel name.
>> >   https://lore.kernel.org/kvm/20221205233235.622491-3-
>> kim.phillips@amd.com/
>> >
>> > v1:
>> https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit
>> @bmoger-ubuntu/
>> >
>> >
>> > Babu Moger (3):
>> >   target/i386: Add a couple of feature bits in 8000_0008_EBX
>> >   target/i386: Add feature bits for CPUID_Fn80000021_EAX
>> >   target/i386: Add missing feature bits in EPYC-Milan model
>> >
>> > Michael Roth (2):
>> >   target/i386: allow versioned CPUs to specify new cache_info
>> >   target/i386: Add new EPYC CPU versions with updated cache_info
>> >
>> >  target/i386/cpu.c | 252
>> +++++++++++++++++++++++++++++++++++++++++++++-
>> >  target/i386/cpu.h |  12 +++
>> >  2 files changed, 259 insertions(+), 5 deletions(-)
>> >
>> > --
>> > 2.34.1
> 

-- 
Thanks
Babu Moger

Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

[Moger, Babu]

Hi Paolo,
Any plans to merge these patches to v8.0 release.
Thanks
Babu

On 3/1/23 14:01, Moger, Babu wrote:
> Gentle ping again. Hope this patch doesn't get lost.
> Thanks
> Babu
> 
> On 1/31/23 14:21, Moger, Babu wrote:
>>
>>> -----Original Message-----
>>> From: Michael S. Tsirkin <mst@redhat.com>
>>> Sent: Friday, January 27, 2023 6:53 AM
>>> To: Moger, Babu <Babu.Moger@amd.com>
>>> Cc: pbonzini@redhat.com; mtosatti@redhat.com; kvm@vger.kernel.org;
>>> marcel.apfelbaum@gmail.com; imammedo@redhat.com;
>>> richard.henderson@linaro.org; yang.zhong@intel.com; jing2.liu@intel.com;
>>> vkuznets@redhat.com; Roth, Michael <Michael.Roth@amd.com>; Huang2, Wei
>>> <Wei.Huang2@amd.com>
>>> Subject: Re: [PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models
>>>
>>> On Fri, Jan 06, 2023 at 12:56:55PM -0600, Babu Moger wrote:
>>>> This series adds following changes.
>>>> a. Allow versioned CPUs to specify new cache_info pointers.
>>>> b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
>>>>     cache_info.complex_indexing.
>>>> c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
>>>
>>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>>
>> Michael, Thank you
>>
>>>
>>> who's merging this btw?
>>> target/i386/cpu.c doesn't have an official maintainer in MAINTAINERS ...
>>
>> I thought Paolo might pick this up.
>>
>> Thanks
>> Babu
>>
>>>
>>>> ---
>>>> v2:
>>>>    Refreshed the patches on top of latest master.
>>>>    Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE
>>> to
>>>>    match the kernel name.
>>>>    https://lore.kernel.org/kvm/20221205233235.622491-3-
>>> kim.phillips@amd.com/
>>>>
>>>> v1:
>>> https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit
>>> @bmoger-ubuntu/
>>>>
>>>>
>>>> Babu Moger (3):
>>>>    target/i386: Add a couple of feature bits in 8000_0008_EBX
>>>>    target/i386: Add feature bits for CPUID_Fn80000021_EAX
>>>>    target/i386: Add missing feature bits in EPYC-Milan model
>>>>
>>>> Michael Roth (2):
>>>>    target/i386: allow versioned CPUs to specify new cache_info
>>>>    target/i386: Add new EPYC CPU versions with updated cache_info
>>>>
>>>>   target/i386/cpu.c | 252
>>> +++++++++++++++++++++++++++++++++++++++++++++-
>>>>   target/i386/cpu.h |  12 +++
>>>>   2 files changed, 259 insertions(+), 5 deletions(-)
>>>>
>>>> --
>>>> 2.34.1
>>
> 

-- 
Thanks
Babu Moger