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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id bg21-20020a05600c3c9500b003db06493ee7sm17491455wmb.47.2023.02.06.03.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 03:54:46 -0800 (PST) Date: Mon, 6 Feb 2023 12:54:45 +0100 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Albert Ou , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: Re: [PATCH v5 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Message-ID: <20230206115445.4deembtvetojslee@orel> References: <20230205011515.1284674-1-atishp@rivosinc.com> <20230205011515.1284674-12-atishp@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230205011515.1284674-12-atishp@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Sat, Feb 04, 2023 at 05:15:12PM -0800, Atish Patra wrote: > As the KVM guests only see the virtual PMU counters, all hpmcounter > access should trap and KVM emulates the read access on behalf of guests. > > Reviewed-by: Andrew Jones > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/kvm_vcpu_pmu.h | 16 ++++++++ > arch/riscv/kvm/vcpu_insn.c | 4 +- > arch/riscv/kvm/vcpu_pmu.c | 59 ++++++++++++++++++++++++++- > 3 files changed, 77 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h > index 40905db..344a3ad 100644 > --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h > +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h > @@ -48,6 +48,19 @@ struct kvm_pmu { > #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) > #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu_context)) > > +#if defined(CONFIG_32BIT) > +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ > +{.base = CSR_CYCLEH, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, \ > +{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, ^ should be tabs? > +#else > +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ > +{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, ^ here too > +#endif > + > +int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num, > + unsigned long *val, unsigned long new_val, > + unsigned long wr_mask); > + > int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata); > int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, > struct kvm_vcpu_sbi_return *retdata); > @@ -71,6 +84,9 @@ void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); > struct kvm_pmu { > }; > > +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ > +{ .base = 0, .count = 0, .func = NULL }, ^ and here and aligned with the ones above? Thanks, drew