From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
Han-Kuan Chen <hankuan.chen@sifive.com>,
Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Nicolas Saenz Julienne <nsaenzju@redhat.com>,
Frederic Weisbecker <frederic@kernel.org>,
Andrew Bresticker <abrestic@rivosinc.com>,
Jisheng Zhang <jszhang@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
Masahiro Yamada <masahiroy@kernel.org>
Subject: [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself
Date: Fri, 17 Mar 2023 11:35:24 +0000 [thread overview]
Message-ID: <20230317113538.10878-6-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
Disable vector instructions execution for kernel mode at its entrances.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/kernel/entry.S | 6 +++---
arch/riscv/kernel/head.S | 12 ++++++------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 99d38fdf8b18..e38676d9a0d6 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -77,10 +77,10 @@ _save_context:
* Disable user-mode memory access as it should only be set in the
* actual user copy routines.
*
- * Disable the FPU to detect illegal usage of floating point in kernel
- * space.
+ * Disable the FPU/Vector to detect illegal usage of floating point
+ * or vector in kernel space.
*/
- li t0, SR_SUM | SR_FS
+ li t0, SR_SUM | SR_FS_VS
REG_L s0, TASK_TI_USER_SP(tp)
csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3fd6a4bd9c3e..e16bb2185d55 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -140,10 +140,10 @@ secondary_start_sbi:
.option pop
/*
- * Disable FPU to detect illegal usage of
- * floating point in kernel space
+ * Disable FPU & VECTOR to detect illegal usage of
+ * floating point or vector in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS_VS
csrc CSR_STATUS, t0
/* Set trap vector to spin forever to help debug */
@@ -234,10 +234,10 @@ pmp_done:
.option pop
/*
- * Disable FPU to detect illegal usage of
- * floating point in kernel space
+ * Disable FPU & VECTOR to detect illegal usage of
+ * floating point or vector in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS_VS
csrc CSR_STATUS, t0
#ifdef CONFIG_RISCV_BOOT_SPINWAIT
--
2.17.1
next prev parent reply other threads:[~2023-03-17 11:37 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-17 11:35 [PATCH -next v15 00/19] riscv: Add vector ISA support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 01/19] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-17 11:35 ` Andy Chiu [this message]
2023-03-17 11:35 ` [PATCH -next v15 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-03-20 13:02 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-20 13:05 ` Conor Dooley
2023-03-20 14:46 ` Andy Chiu
2023-03-20 14:54 ` Conor Dooley
2023-03-22 1:54 ` Guo Ren
2023-03-23 10:21 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-20 13:07 ` Conor Dooley
2023-03-23 10:23 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-20 13:27 ` Conor Dooley
2023-03-23 10:29 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-20 13:36 ` Conor Dooley
2023-03-23 7:50 ` Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-23 10:36 ` Björn Töpel
2023-03-23 14:39 ` Guo Ren
2023-03-17 11:35 ` [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-20 13:40 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-17 11:54 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-17 12:02 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-03-17 15:46 ` Nathan Chancellor
2023-03-20 13:47 ` Conor Dooley
2023-03-23 10:44 ` [PATCH -next v15 00/19] riscv: Add vector ISA support Björn Töpel
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