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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Jintack Lim <jintack@cs.columbia.edu>,
	Russell King <rmk+kernel@armlinux.org.uk>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v10 15/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg()
Date: Mon, 15 May 2023 18:30:19 +0100	[thread overview]
Message-ID: <20230515173103.1017669-16-maz@kernel.org> (raw)
In-Reply-To: <20230515173103.1017669-1-maz@kernel.org>

KVM internally uses accessor functions when reading or writing the
guest's system registers. This takes care of accessing either the stored
copy or using the "live" EL1 system registers when the host uses VHE.

With the introduction of virtual EL2 we add a bunch of EL2 system
registers, which now must also be taken care of:
- If the guest is running in vEL2, and we access an EL1 sysreg, we must
  revert to the stored version of that, and not use the CPU's copy.
- If the guest is running in vEL1, and we access an EL2 sysreg, we must
  also use the stored version, since the CPU carries the EL1 copy.
- Some EL2 system registers are supposed to affect the current execution
  of the system, so we need to put them into their respective EL1
  counterparts. For this we need to define a mapping between the two.
  This is done using the newly introduced struct el2_sysreg_map.
- Some EL2 system registers have a different format than their EL1
  counterpart, so we need to translate them before writing them to the
  CPU. This is done using an (optional) translate function in the map.
- There are the three special registers SP_EL2, SPSR_EL2 and ELR_EL2,
  which need some separate handling (SPSR_EL2 is being handled in a
  separate patch).

All of these cases are now wrapped into the existing accessor functions,
so KVM users wouldn't need to care whether they access EL2 or EL1
registers and also which state the guest is in.

This handles what was formerly known as the "shadow state" dynamically,
without requiring a separate copy for each vCPU EL.

Reviewed-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Co-developed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 143 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 138 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 77f8bc64148a..6e5783655b03 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -63,24 +63,157 @@ static bool write_to_read_only(struct kvm_vcpu *vcpu,
 	return false;
 }
 
+#define PURE_EL2_SYSREG(el2)						\
+	case el2: {							\
+		*el1r = el2;						\
+		return true;						\
+	}
+
+#define MAPPED_EL2_SYSREG(el2, el1, fn)					\
+	case el2: {							\
+		*xlate = fn;						\
+		*el1r = el1;						\
+		return true;						\
+	}
+
+static bool get_el2_to_el1_mapping(unsigned int reg,
+				   unsigned int *el1r, u64 (**xlate)(u64))
+{
+	switch (reg) {
+		PURE_EL2_SYSREG(  VPIDR_EL2	);
+		PURE_EL2_SYSREG(  VMPIDR_EL2	);
+		PURE_EL2_SYSREG(  ACTLR_EL2	);
+		PURE_EL2_SYSREG(  HCR_EL2	);
+		PURE_EL2_SYSREG(  MDCR_EL2	);
+		PURE_EL2_SYSREG(  HSTR_EL2	);
+		PURE_EL2_SYSREG(  HACR_EL2	);
+		PURE_EL2_SYSREG(  VTTBR_EL2	);
+		PURE_EL2_SYSREG(  VTCR_EL2	);
+		PURE_EL2_SYSREG(  RVBAR_EL2	);
+		PURE_EL2_SYSREG(  TPIDR_EL2	);
+		PURE_EL2_SYSREG(  HPFAR_EL2	);
+		PURE_EL2_SYSREG(  ELR_EL2	);
+		PURE_EL2_SYSREG(  SPSR_EL2	);
+		PURE_EL2_SYSREG(  CNTHCTL_EL2	);
+		MAPPED_EL2_SYSREG(SCTLR_EL2,   SCTLR_EL1,
+				  translate_sctlr_el2_to_sctlr_el1	     );
+		MAPPED_EL2_SYSREG(CPTR_EL2,    CPACR_EL1,
+				  translate_cptr_el2_to_cpacr_el1	     );
+		MAPPED_EL2_SYSREG(TTBR0_EL2,   TTBR0_EL1,
+				  translate_ttbr0_el2_to_ttbr0_el1	     );
+		MAPPED_EL2_SYSREG(TTBR1_EL2,   TTBR1_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(TCR_EL2,     TCR_EL1,
+				  translate_tcr_el2_to_tcr_el1		     );
+		MAPPED_EL2_SYSREG(VBAR_EL2,    VBAR_EL1,    NULL	     );
+		MAPPED_EL2_SYSREG(AFSR0_EL2,   AFSR0_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(AFSR1_EL2,   AFSR1_EL1,   NULL	     );
+		MAPPED_EL2_SYSREG(ESR_EL2,     ESR_EL1,     NULL	     );
+		MAPPED_EL2_SYSREG(FAR_EL2,     FAR_EL1,     NULL	     );
+		MAPPED_EL2_SYSREG(MAIR_EL2,    MAIR_EL1,    NULL	     );
+		MAPPED_EL2_SYSREG(AMAIR_EL2,   AMAIR_EL1,   NULL	     );
+	default:
+		return false;
+	}
+}
+
 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
 {
 	u64 val = 0x8badf00d8badf00d;
+	u64 (*xlate)(u64) = NULL;
+	unsigned int el1r;
 
-	if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
-	    __vcpu_read_sys_reg_from_cpu(reg, &val))
+	if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
+		goto memory_read;
+
+	if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
+		if (!is_hyp_ctxt(vcpu))
+			goto memory_read;
+
+		/*
+		 * ELR_EL2 is special cased for now.
+		 */
+		switch (reg) {
+		case ELR_EL2:
+			return read_sysreg_el1(SYS_ELR);
+		}
+
+		/*
+		 * If this register does not have an EL1 counterpart,
+		 * then read the stored EL2 version.
+		 */
+		if (reg == el1r)
+			goto memory_read;
+
+		/*
+		 * If we have a non-VHE guest and that the sysreg
+		 * requires translation to be used at EL1, use the
+		 * in-memory copy instead.
+		 */
+		if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
+			goto memory_read;
+
+		/* Get the current version of the EL1 counterpart. */
+		WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
+		return val;
+	}
+
+	/* EL1 register can't be on the CPU if the guest is in vEL2. */
+	if (unlikely(is_hyp_ctxt(vcpu)))
+		goto memory_read;
+
+	if (__vcpu_read_sys_reg_from_cpu(reg, &val))
 		return val;
 
+memory_read:
 	return __vcpu_sys_reg(vcpu, reg);
 }
 
 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 {
-	if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
-	    __vcpu_write_sys_reg_to_cpu(val, reg))
+	u64 (*xlate)(u64) = NULL;
+	unsigned int el1r;
+
+	if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
+		goto memory_write;
+
+	if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
+		if (!is_hyp_ctxt(vcpu))
+			goto memory_write;
+
+		/*
+		 * Always store a copy of the write to memory to avoid having
+		 * to reverse-translate virtual EL2 system registers for a
+		 * non-VHE guest hypervisor.
+		 */
+		__vcpu_sys_reg(vcpu, reg) = val;
+
+		switch (reg) {
+		case ELR_EL2:
+			write_sysreg_el1(val, SYS_ELR);
+			return;
+		}
+
+		/* No EL1 counterpart? We're done here.? */
+		if (reg == el1r)
+			return;
+
+		if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
+			val = xlate(val);
+
+		/* Redirect this to the EL1 version of the register. */
+		WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
+		return;
+	}
+
+	/* EL1 register can't be on the CPU if the guest is in vEL2. */
+	if (unlikely(is_hyp_ctxt(vcpu)))
+		goto memory_write;
+
+	if (__vcpu_write_sys_reg_to_cpu(val, reg))
 		return;
 
-	__vcpu_sys_reg(vcpu, reg) = val;
+memory_write:
+	 __vcpu_sys_reg(vcpu, reg) = val;
 }
 
 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
-- 
2.34.1


  parent reply	other threads:[~2023-05-15 17:49 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-15 17:30 [PATCH v10 00/59] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 01/59] KVM: arm64: Move VTCR_EL2 into struct s2_mmu Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 02/59] arm64: Add missing Set/Way CMO encodings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 03/59] arm64: Add missing VA " Marc Zyngier
2023-06-05 17:46   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 04/59] arm64: Add missing ERXMISCx_EL1 encodings Marc Zyngier
2023-06-05 17:47   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 05/59] arm64: Add missing DC ZVA/GVA/GZVA encodings Marc Zyngier
2023-06-05 17:47   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 06/59] arm64: Add TLBI operation encodings Marc Zyngier
2023-06-06  9:33   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 07/59] arm64: Add AT " Marc Zyngier
2023-06-14 15:08   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 08/59] KVM: arm64: Add missing HCR_EL2 trap bits Marc Zyngier
2023-06-14 15:08   ` Eric Auger
2023-05-15 17:30 ` [PATCH v10 09/59] KVM: arm64: nv: Add trap forwarding infrastructure Marc Zyngier
2023-07-13 14:29   ` Eric Auger
2023-07-14 10:53     ` Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 10/59] KVM: arm64: nv: Add trap forwarding for HCR_EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 11/59] KVM: arm64: nv: Expose FEAT_EVT to nested guests Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 12/59] KVM: arm64: nv: Add trap forwarding for MDCR_EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 13/59] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 14/59] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier
2023-05-15 17:30 ` Marc Zyngier [this message]
2023-05-15 17:30 ` [PATCH v10 16/59] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 17/59] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 18/59] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 19/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 20/59] KVM: arm64: nv: Trap CPACR_EL1 access " Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 21/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 22/59] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 23/59] KVM: arm64: nv: Respect virtual HCR_EL2.{NV,TSC) settings Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 24/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 25/59] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 26/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 27/59] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 28/59] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 29/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2023-09-14 13:10   ` Ganapatrao Kulkarni
2023-09-14 13:37     ` Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 30/59] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 31/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 32/59] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 33/59] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 34/59] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 35/59] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 36/59] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 37/59] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 38/59] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 39/59] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 40/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 41/59] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 42/59] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 43/59] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 44/59] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 45/59] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 46/59] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 47/59] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 48/59] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 49/59] KVM: arm64: nv: Move nested vgic state into the sysreg file Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 50/59] KVM: arm64: Add FEAT_NV2 cpu feature Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 51/59] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 52/59] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 53/59] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 54/59] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2023-05-15 17:30 ` [PATCH v10 55/59] KVM: arm64: nv: Enable ARMv8.4-NV support Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 56/59] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 57/59] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 58/59] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2023-05-15 17:31 ` [PATCH v10 59/59] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier
2023-05-16 16:53 ` [PATCH v10 00/59] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Eric Auger
2023-05-16 18:47   ` Marc Zyngier
2023-05-16 20:28   ` Marc Zyngier
2023-05-17  8:59     ` Eric Auger
2023-05-17 14:12       ` Marc Zyngier
2023-06-06  9:33         ` Eric Auger
2023-06-06 16:30           ` Marc Zyngier
2023-06-07 16:39             ` Eric Auger
2023-06-06 17:52           ` Miguel Luis
2023-06-07 16:40             ` Eric Auger
2023-06-10  8:25               ` Miguel Luis
2023-06-11 16:28                 ` Eric Auger
2023-06-05 11:28 ` Eric Auger
2023-06-06  7:30   ` Marc Zyngier
2023-06-06  9:29     ` Eric Auger
2023-06-06 16:22       ` Marc Zyngier
2023-06-07 16:30         ` Eric Auger
2023-06-28  6:45 ` Ganapatrao Kulkarni
2023-06-29  7:03   ` Marc Zyngier
2023-07-04 12:31     ` Ganapatrao Kulkarni
2023-07-07  9:46       ` Ganapatrao Kulkarni
2023-07-11 11:56         ` Ganapatrao Kulkarni
2023-07-11 12:30           ` Marc Zyngier
2023-07-10 12:56     ` Miguel Luis
2023-07-18 10:29       ` Miguel Luis

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