From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
julien.thierry.kdev@gmail.com, maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 4/8] riscv: Sort the ISA extension array alphabetically
Date: Mon, 5 Jun 2023 19:32:04 +0530 [thread overview]
Message-ID: <20230605140208.272027-5-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230605140208.272027-1-apatel@ventanamicro.com>
Let us follow alphabetical order for listing ISA extensions in
the isa_info_arr[] array.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/fdt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/riscv/fdt.c b/riscv/fdt.c
index 3cdb95c..977e962 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -15,11 +15,12 @@ struct isa_ext_info {
};
struct isa_ext_info isa_info_arr[] = {
- {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
+ /* sorted alphabetically */
{"sstc", KVM_RISCV_ISA_EXT_SSTC},
{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
- {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
+ {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
+ {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
};
static void dump_fdt(const char *dtb_file, void *fdt)
--
2.34.1
next prev parent reply other threads:[~2023-06-05 14:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 14:02 [PATCH v2 0/8] RISC-V SBI enable/disable, Zbb, Zicboz, and Ssaia support Anup Patel
2023-06-05 14:02 ` [PATCH v2 1/8] Sync-up headers with Linux-6.4-rc5 Anup Patel
2023-07-06 14:33 ` Will Deacon
2023-07-06 17:17 ` Anup Patel
2023-06-05 14:02 ` [PATCH v2 2/8] riscv: Allow setting custom mvendorid, marchid, and mimpid Anup Patel
2023-06-05 14:02 ` [PATCH v2 3/8] riscv: Allow disabling SBI extensions for Guest Anup Patel
2023-06-05 14:02 ` Anup Patel [this message]
2023-06-05 14:02 ` [PATCH v2 5/8] riscv: Add zbb extension support Anup Patel
2023-06-05 14:02 ` [PATCH v2 6/8] riscv: Add Zicboz " Anup Patel
2023-06-05 14:02 ` [PATCH v2 7/8] riscv: Add Ssaia " Anup Patel
2023-06-05 14:02 ` [PATCH v2 8/8] riscv: Fix guest RAM alloc size computation for RV32 Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230605140208.272027-5-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=julien.thierry.kdev@gmail.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=maz@kernel.org \
--cc=pbonzini@redhat.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox