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Fri, 23 Jun 2023 07:43:17 -0700 (PDT) Received: from localhost ([192.55.54.50]) by smtp.gmail.com with ESMTPSA id jn9-20020a170903050900b001b19d14a3d5sm7309227plb.68.2023.06.23.07.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:43:16 -0700 (PDT) Date: Fri, 23 Jun 2023 07:43:15 -0700 From: Isaku Yamahata To: "Huang, Kai" Cc: "isaku.yamahata@gmail.com" , "tglx@linutronix.de" , "liam.merwick@oracle.com" , "tobin@ibm.com" , "alpergun@google.com" , "Luck, Tony" , "jmattson@google.com" , "Lutomirski, Andy" , "ak@linux.intel.com" , "pbonzini@redhat.com" , "kvm@vger.kernel.org" , "srinivas.pandruvada@linux.intel.com" , "slp@redhat.com" , "dovmurik@linux.ibm.com" , "michael.roth@amd.com" , "peterz@infradead.org" , "linux-kernel@vger.kernel.org" , "pgonda@google.com" , "thomas.lendacky@amd.com" , "rientjes@google.com" , "Wang, Zhi A" , "x86@kernel.org" , "bp@alien8.de" , "Annapurve, Vishal" , "dgilbert@redhat.com" , "Christopherson,, Sean" , "vkuznets@redhat.com" , "marcorr@google.com" , "vbabka@suse.cz" , "ashish.kalra@amd.com" , "linux-coco@lists.linux.dev" , "nikunj.dadhania@amd.com" , "Rodel, Jorg" , "mingo@redhat.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "hpa@zytor.com" , "kirill@shutemov.name" , "jarkko@kernel.org" , "ardb@kernel.org" , "linux-crypto@vger.kernel.org" , "linux-mm@kvack.org" , "dave.hansen@linux.intel.com" Subject: Re: [PATCH RFC v9 04/51] KVM: x86: Determine shared/private faults using a configurable mask Message-ID: <20230623144315.GC3436214@ls.amr.corp.intel.com> References: <20230612042559.375660-5-michael.roth@amd.com> <20230614164709.GT2244082@ls.amr.corp.intel.com> <20230620202841.7qizls3u3kcck45g@amd.com> <20230620211845.GV2244082@ls.amr.corp.intel.com> <20230621230031.37hdnymbjzwjgbo2@amd.com> <20230622153229.vjkrzi6rgiolstns@amd.com> <25037dfe969698dd109daee8c6dbe0d08a874a08.camel@intel.com> <20230622233906.GA3436214@ls.amr.corp.intel.com> <5ec0664fe81df54019ef5934f2dc6dfadf1d649c.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <5ec0664fe81df54019ef5934f2dc6dfadf1d649c.camel@intel.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Jun 22, 2023 at 11:52:56PM +0000, "Huang, Kai" wrote: > On Thu, 2023-06-22 at 16:39 -0700, Isaku Yamahata wrote: > > On Thu, Jun 22, 2023 at 10:31:08PM +0000, > > "Huang, Kai" wrote: > > > > > > If there are better ways to handle *how* > > > > that's done I don't have any complaints there, but moving/adding bits > > > > to GPA/error_flags after fault time just seems unecessary to me when > > > > fault->is_private field can serve that purpose just as well. > > > > > > Perhaps you missed my point. My point is arch.mmu_private_fault_mask and > > > arch.gfn_shared_mask seem redundant because the logic around them are exactly > > > the same. I do believe we should have fault->is_private passing to the common > > > MMU code. > > > > > > In fact, now I am wondering why we need to have "mmu_private_fault_mask" and > > > "gfn_shared_mask" in _common_ KVM MMU code. We already have enough mechanism in > > > KVM common code: > > > > > > 1) fault->is_private > > > 2) kvm_mmu_page_role.private > > > 3) an Xarray to tell whether a GFN is private or shared > > > > > > I am not convinced that we need to have "mmu_private_fault_mask" and > > > "gfn_shared_mask" in common KVM MMU code. Instead, they can be in AMD and > > > Intel's vendor code. > > > > > > Maybe it makes sense to have "gfn_shared_mask" in the KVM common code so that > > > the fault handler can just strip away the "shared bit" at the very beginning (at > > > least for TDX), but for the rest of the time I think we should already have > > > enough infrastructure to handle private/shared mapping. > > > > > > Btw, one minor issue is, if I recall correctly, for TDX the shared bit must be > > > applied to the GFN for shared mapping in normal EPT. I guess AMD doesn't need > > > that for shared mapping. So "gfn_shared_mask" maybe useful in this case, but > > > w/o it I believe we can also achieve in another way via vendor callback. > > > > > > "2) kvm_mmu_page_role.private" above has different meaning. > > > > a). The fault is private or not. > > b). page table the fault handler is walking is private or conventional. > > > > a.) is common for SNP, TDX and PROTECTED_VM. It makes sense in > > kvm_mmu_do_page_fault() and __kvm_faultin_pfn(). After kvm_faultin_pfn(), the > > fault handler can mostly forget it for SNP and PROTECTED_VM. (large page > > adjustment needs it, though.) This is what we're discussing in this thread. > > > > b.) is specific to TDX. TDX KVM MMU introduces one more page table. > > > > > > I don't buy the last sentence. Even it's not necessarily for AMD from > hardware's perspective, but the concept remains true for AMD too. So why cannot > we use it for AMD? We can use it for AMD. Let me rephrase it. TDX only uses it now. SEV-SNP may or may not use it at their option. -- Isaku Yamahata