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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id a12-20020a1709064a4c00b009932337747esm4805726ejv.86.2023.07.04.07.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 07:46:19 -0700 (PDT) Date: Tue, 4 Jul 2023 16:46:18 +0200 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Paolo Bonzini , kvm@vger.kernel.org Subject: Re: [PATCH v4 3/6] target/riscv: check the in-kernel irqchip support Message-ID: <20230704-27481846a2cab7364d040a19@orel> References: <20230621145500.25624-1-yongxuan.wang@sifive.com> <20230621145500.25624-4-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230621145500.25624-4-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Jun 21, 2023 at 02:54:53PM +0000, Yong-Xuan Wang wrote: > We check the in-kernel irqchip support when using KVM acceleration. > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu > Reviewed-by: Daniel Henrique Barboza > --- > target/riscv/kvm.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 0f932a5b96..eb469e8ca5 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -433,7 +433,18 @@ int kvm_arch_init(MachineState *ms, KVMState *s) > > int kvm_arch_irqchip_create(KVMState *s) > { > - return 0; > + if (kvm_kernel_irqchip_split()) { > + error_report("-machine kernel_irqchip=split is not supported " > + "on RISC-V."); It's best to not split error messages across lines. We can go to 90 chars before checkpatch considers it an error, and I'd still consider it worse to split an error message than to ignore checkpatch and exceed 90 chars. > + exit(1); > + } > + > + /* > + * If we can create the VAIA using the newer device control API, we > + * let the device do this when it initializes itself, otherwise we > + * fall back to the old API This comment appears lifted from arm, but the "fall back to the old API" doesn't apply to riscv since riscv doesn't support KVM_CREATE_IRQCHIP. > + */ > + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); > } > > int kvm_arch_process_async_events(CPUState *cs) > -- > 2.17.1 > > Thanks, drew