From: Jinrong Liang <ljr.kernel@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Like Xu <likexu@tencent.com>,
David Matlack <dmatlack@google.com>,
Aaron Lewis <aaronlewis@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jinrong Liang <cloudliang@tencent.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 11/11] KVM: selftests: Test AMD Guest PerfMonV2
Date: Mon, 14 Aug 2023 19:51:08 +0800 [thread overview]
Message-ID: <20230814115108.45741-12-cloudliang@tencent.com> (raw)
In-Reply-To: <20230814115108.45741-1-cloudliang@tencent.com>
From: Jinrong Liang <cloudliang@tencent.com>
Add test case for AMD Guest PerfMonV2. Also test Intel
MSR_CORE_PERF_GLOBAL_STATUS and MSR_CORE_PERF_GLOBAL_OVF_CTRL.
Signed-off-by: Jinrong Liang <cloudliang@tencent.com>
---
.../kvm/x86_64/pmu_basic_functionality_test.c | 48 ++++++++++++++++++-
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
index cb2a7ad5c504..02bd1fe3900b 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
@@ -58,7 +58,9 @@ static uint64_t run_vcpu(struct kvm_vcpu *vcpu, uint64_t *ucall_arg)
static void guest_measure_loop(uint64_t event_code)
{
+ uint64_t global_ovf_ctrl_msr, global_status_msr, global_ctrl_msr;
uint8_t nr_gp_counters, pmu_version = 1;
+ uint8_t gp_counter_bit_width = 48;
uint64_t event_sel_msr;
uint32_t counter_msr;
unsigned int i;
@@ -68,6 +70,12 @@ static void guest_measure_loop(uint64_t event_code)
pmu_version = this_cpu_property(X86_PROPERTY_PMU_VERSION);
event_sel_msr = MSR_P6_EVNTSEL0;
+ if (pmu_version > 1) {
+ global_ovf_ctrl_msr = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
+ global_status_msr = MSR_CORE_PERF_GLOBAL_STATUS;
+ global_ctrl_msr = MSR_CORE_PERF_GLOBAL_CTRL;
+ }
+
if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES)
counter_msr = MSR_IA32_PMC0;
else
@@ -76,6 +84,17 @@ static void guest_measure_loop(uint64_t event_code)
nr_gp_counters = AMD64_NR_COUNTERS;
event_sel_msr = MSR_K7_EVNTSEL0;
counter_msr = MSR_K7_PERFCTR0;
+
+ if (this_cpu_has(X86_FEATURE_AMD_PMU_EXT_CORE) &&
+ this_cpu_has(X86_FEATURE_AMD_PERFMON_V2)) {
+ nr_gp_counters = this_cpu_property(X86_PROPERTY_AMD_PMU_NR_CORE_COUNTERS);
+ global_ovf_ctrl_msr = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR;
+ global_status_msr = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS;
+ global_ctrl_msr = MSR_AMD64_PERF_CNTR_GLOBAL_CTL;
+ event_sel_msr = MSR_F15H_PERF_CTL0;
+ counter_msr = MSR_F15H_PERF_CTR0;
+ pmu_version = 2;
+ }
}
for (i = 0; i < nr_gp_counters; i++) {
@@ -84,14 +103,39 @@ static void guest_measure_loop(uint64_t event_code)
ARCH_PERFMON_EVENTSEL_ENABLE | event_code);
if (pmu_version > 1) {
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i));
+ wrmsr(global_ctrl_msr, BIT_ULL(i));
__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+ wrmsr(global_ctrl_msr, 0);
GUEST_SYNC(_rdpmc(i));
} else {
__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
GUEST_SYNC(_rdpmc(i));
}
+
+ if (pmu_version > 1 && _rdpmc(i)) {
+ wrmsr(global_ctrl_msr, 0);
+ wrmsr(counter_msr + i, 0);
+ __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+ GUEST_ASSERT(!_rdpmc(i));
+
+ wrmsr(global_ctrl_msr, BIT_ULL(i));
+ __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+ GUEST_ASSERT(_rdpmc(i));
+
+ if (host_cpu_is_intel)
+ gp_counter_bit_width =
+ this_cpu_property(X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH);
+
+ wrmsr(global_ctrl_msr, 0);
+ wrmsr(counter_msr + i, (1ULL << gp_counter_bit_width) - 2);
+ wrmsr(global_ctrl_msr, BIT_ULL(i));
+ __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+ GUEST_ASSERT(rdmsr(global_status_msr) & BIT_ULL(i));
+
+ wrmsr(global_ctrl_msr, 0);
+ wrmsr(global_ovf_ctrl_msr, BIT_ULL(i));
+ GUEST_ASSERT(!(rdmsr(global_status_msr) & BIT_ULL(i)));
+ }
}
if (host_cpu_is_amd || pmu_version < 2)
--
2.39.3
prev parent reply other threads:[~2023-08-14 11:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-14 11:50 [PATCH v3 00/11] KVM: selftests: Test the consistency of the PMU's CPUID and its features Jinrong Liang
2023-08-14 11:50 ` [PATCH v3 01/11] KVM: selftests: Add vcpu_set_cpuid_property() to set properties Jinrong Liang
2023-08-14 11:50 ` [PATCH v3 02/11] KVM: selftests: Add pmu.h for PMU events and common masks Jinrong Liang
2023-08-17 22:32 ` Sean Christopherson
2023-08-21 8:56 ` Like Xu
2023-08-21 9:07 ` Jinrong Liang
2023-08-14 11:51 ` [PATCH v3 03/11] KVM: selftests: Test Intel PMU architectural events on gp counters Jinrong Liang
2023-08-17 22:46 ` Sean Christopherson
2023-08-17 22:54 ` Sean Christopherson
2023-08-21 11:45 ` Jinrong Liang
2023-08-14 11:51 ` [PATCH v3 04/11] KVM: selftests: Test Intel PMU architectural events on fixed counters Jinrong Liang
2023-08-17 22:56 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 05/11] KVM: selftests: Test consistency of CPUID with num of gp counters Jinrong Liang
2023-08-17 23:00 ` Sean Christopherson
2023-08-17 23:18 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 06/11] KVM: selftests: Test consistency of CPUID with num of fixed counters Jinrong Liang
2023-08-17 23:04 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 07/11] KVM: selftests: Test Intel supported fixed counters bit mask Jinrong Liang
2023-08-17 23:19 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 08/11] KVM: selftests: Test consistency of PMU MSRs with Intel PMU version Jinrong Liang
2023-08-17 23:21 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 09/11] KVM: selftests: Add x86 feature and properties for AMD PMU in processor.h Jinrong Liang
2023-08-17 23:26 ` Sean Christopherson
2023-08-14 11:51 ` [PATCH v3 10/11] KVM: selftests: Test AMD PMU events on legacy four performance counters Jinrong Liang
2023-08-14 11:51 ` Jinrong Liang [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230814115108.45741-12-cloudliang@tencent.com \
--to=ljr.kernel@gmail.com \
--cc=aaronlewis@google.com \
--cc=cloudliang@tencent.com \
--cc=dmatlack@google.com \
--cc=kvm@vger.kernel.org \
--cc=likexu@tencent.com \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox