From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8D39CD98FD for ; Wed, 11 Oct 2023 08:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344742AbjJKIRV (ORCPT ); Wed, 11 Oct 2023 04:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230179AbjJKIRU (ORCPT ); Wed, 11 Oct 2023 04:17:20 -0400 Received: from out-199.mta1.migadu.com (out-199.mta1.migadu.com [95.215.58.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F35C93 for ; Wed, 11 Oct 2023 01:17:18 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1697012236; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m/P2cXWXKHxiKIrHs6BVDT2TzNGuicu3kg1x643elmo=; b=fI2e3O2CpjLkohDlSCvitB3OpjTRFNOfdJtfu703Z85lVSCv4t3gBkVUM4Vfg6v7GgaBy5 LzI0tIPRPDT1AnFQpb/3fWRPTdK7PrTLkeNSGZzrhEF/VsFuumyY7qbPoLmidASbJOKYJq 1TzqA43oxEmdbQoeO1rov+LAVtBNWCs= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , Raghavendra Rao Ananta , Mark Rutland , Will Deacon , James Clark , Oliver Upton Subject: [PATCH 2/2] KVM: arm64: Treat PMEVTYPER_EL0.NSH as RES0 Date: Wed, 11 Oct 2023 08:16:48 +0000 Message-ID: <20231011081649.3226792-3-oliver.upton@linux.dev> In-Reply-To: <20231011081649.3226792-1-oliver.upton@linux.dev> References: <20231011081649.3226792-1-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Prevent the guest from setting the NSH bit, which enables event counting while the PE is in EL2. kvm_pmu_create_perf_event() never wired up the bit, nor does it make any sense in the context of a guest without NV. While at it, build the event type mask using explicit field definitions instead of relying on ARMV8_PMU_EVTYPE_MASK. KVM probably should've been doing this in the first place, as it avoids changes to the aforementioned mask affecting sysreg emulation. Signed-off-by: Oliver Upton --- arch/arm64/kvm/pmu-emul.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 0666212c0c15..087764435390 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -663,8 +663,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, if (!kvm_vcpu_has_pmu(vcpu)) return; - mask = ARMV8_PMU_EVTYPE_MASK; - mask &= ~ARMV8_PMU_EVTYPE_EVENT; + mask = ARMV8_PMU_EXCLUDE_EL1 | ARMV8_PMU_EXCLUDE_EL0; mask |= kvm_pmu_event_mask(vcpu->kvm); reg = counter_index_to_evtreg(pmc->idx); -- 2.42.0.609.gbb76f46606-goog