From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D76DF9EE for ; Thu, 9 Nov 2023 07:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Nhs0t5CC" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D70C02728 for ; Wed, 8 Nov 2023 23:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699516222; x=1731052222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cErrvaQ2Y2YRcZJb/xIJHbANMmxb80XwPPZKGztP7x4=; b=Nhs0t5CC3FEOgdXXrUbUl6fxQEch6G5d2/lTYwFULaV1wSiWZ0CJfrhz ai64pd33kHQ02BAGDD1QRkbgKrpYDoZkDdfIhRKBlXSkxGqySPNr6wlgQ hJC0OtxngZfy7ReAZHLDgqyoWn8S3FfxiLPhsXjAkS/cj+IHWsSt11DD7 aUemoT5pv6uTdFZ2Yvn2G79q2AL9ng2Yco75loxbXzfVX/7BMKu7rhh7h mSRN4ICun5ndUJrx5y8olX7V+uv6Rqz9hjFFvX4eMfwPkrygZlwZDJ7fj id0AiybK48WDPTW8U6zHyAPtyY38S6Q+mmXrNoMF6AvYNZnLDOM7FgdM+ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="476165136" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="476165136" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2023 23:50:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="763329273" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="763329273" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 08 Nov 2023 23:50:22 -0800 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH v3 2/6] target/i386: mark CR4.FRED not reserved Date: Wed, 8 Nov 2023 23:20:08 -0800 Message-ID: <20231109072012.8078-3-xin3.li@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109072012.8078-1-xin3.li@intel.com> References: <20231109072012.8078-1-xin3.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5faf00551d..e210957cba 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -262,6 +262,12 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) +#ifdef TARGET_X86_64 +#define CR4_FRED_MASK (1ULL << 32) +#else +#define CR4_FRED_MASK 0 +#endif + #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ @@ -269,7 +275,8 @@ typedef enum X86Seg { | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ - | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) + | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \ + | CR4_FRED_MASK)) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2520,6 +2527,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |= CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { + reserved_bits |= CR4_FRED_MASK; + } return reserved_bits; } -- 2.42.0