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From: Jinrong Liang <ljr.kernel@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Like Xu <likexu@tencent.com>,
	Jim Mattson <jmattson@google.com>,
	Aaron Lewis <aaronlewis@google.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Jinrong Liang <cloudliang@tencent.com>,
	Jinrong Liang <ljr.kernel@gmail.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 9/9] KVM: selftests: Test AMD Guest PerfMonV2
Date: Tue, 21 Nov 2023 19:54:57 +0800	[thread overview]
Message-ID: <20231121115457.76269-10-cloudliang@tencent.com> (raw)
In-Reply-To: <20231121115457.76269-1-cloudliang@tencent.com>

From: Jinrong Liang <cloudliang@tencent.com>

Add test case for AMD Guest PerfMonV2.

Signed-off-by: Jinrong Liang <cloudliang@tencent.com>
---
 .../selftests/kvm/x86_64/pmu_counters_test.c  | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
index ca5b352ea6ae..aa44f2282996 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
@@ -722,6 +722,38 @@ static void set_amd_counters(uint8_t *nr_amd_ounters, uint64_t *ctrl_msr,
 	}
 }
 
+static void guest_test_amd_perfmonv2(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < AMD64_NR_COUNTERS_CORE; i++) {
+		wrmsr(MSR_F15H_PERF_CTL0 + i * 2, 0);
+		wrmsr(MSR_F15H_PERF_CTR0 + i * 2, ARCH_PERFMON_EVENTSEL_OS |
+		      ARCH_PERFMON_EVENTSEL_ENABLE | AMD_ZEN_CORE_CYCLES);
+
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
+		__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+		GUEST_ASSERT(!_rdpmc(i));
+
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i));
+		__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
+		GUEST_ASSERT(_rdpmc(i));
+
+		wrmsr(MSR_F15H_PERF_CTL0 + i * 2, (1ULL << 48) - 2);
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 0xff);
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i));
+		__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
+		GUEST_ASSERT(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) &
+			     BIT_ULL(i));
+
+		wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, BIT_ULL(i));
+		GUEST_ASSERT(!(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) &
+			     BIT_ULL(i)));
+	}
+}
+
 static void guest_test_amd_counters(void)
 {
 	bool guest_pmu_is_perfmonv2 = this_cpu_has(X86_FEATURE_PERFMON_V2);
@@ -747,6 +779,9 @@ static void guest_test_amd_counters(void)
 		}
 	}
 
+	if (guest_pmu_is_perfmonv2)
+		guest_test_amd_perfmonv2();
+
 	GUEST_DONE();
 }
 
-- 
2.39.3


  parent reply	other threads:[~2023-11-21 11:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-21 11:54 [PATCH 0/9] Test the consistency of AMD PMU counters and their features Jinrong Liang
2023-11-21 11:54 ` [PATCH 1/9] KVM: selftests: Add forced emulation check to fix #UD Jinrong Liang
2023-11-21 11:54 ` [PATCH 2/9] KVM: selftests: Test gp counters overflow interrupt handling Jinrong Liang
2023-11-21 11:54 ` [PATCH 3/9] KVM: selftests: Test fixed " Jinrong Liang
2023-11-21 11:54 ` [PATCH 4/9] KVM: selftests: Add x86 feature and properties for AMD PMU in processor.h Jinrong Liang
2023-11-21 11:54 ` [PATCH 5/9] KVM: selftests: Test AMD PMU performance counters basic functions Jinrong Liang
2023-11-21 11:54 ` [PATCH 6/9] KVM: selftests: Test consistency of AMD PMU counters num Jinrong Liang
2023-11-21 11:54 ` [PATCH 7/9] KVM: selftests: Test consistency of PMU MSRs with AMD PMU version Jinrong Liang
2023-11-21 11:54 ` [PATCH 8/9] KVM: selftests: Test AMD Guest PerfCtrExtCore Jinrong Liang
2023-11-21 11:54 ` Jinrong Liang [this message]
2024-06-10 23:36 ` [PATCH 0/9] Test the consistency of AMD PMU counters and their features Colton Lewis
2024-06-11  3:48   ` Jinrong Liang

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