From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: Re: [v2 05/10] drivers/perf: riscv: Implement SBI PMU snapshot function
Date: Tue, 9 Jan 2024 18:30:11 +0000 [thread overview]
Message-ID: <20240109-vice-trash-89a4e1a171b2@spud> (raw)
In-Reply-To: <20231229214950.4061381-6-atishp@rivosinc.com>
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On Fri, Dec 29, 2023 at 01:49:45PM -0800, Atish Patra wrote:
> +static noinline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt,
> + unsigned long ctr_ovf_mask)
> +{
> + int idx = 0;
> + struct perf_event *event;
> + unsigned long flag = SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT;
> + u64 max_period, init_val = 0;
> + struct hw_perf_event *hwc;
> + unsigned long ctr_start_mask = 0;
> + struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
> +
> + for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
> + if (ctr_ovf_mask & (1 << idx)) {
> + event = cpu_hw_evt->events[idx];
> + hwc = &event->hw;
> + max_period = riscv_pmu_ctr_get_width_mask(event);
> + init_val = local64_read(&hwc->prev_count) & max_period;
> + sdata->ctr_values[idx] = init_val;
> + }
> + /* We donot need to update the non-overflow counters the previous
> + * value should have been there already.
> + */
One nit for if this is resent, you've got the wrong comment style here.
Otherwise, looks like the things we discussed before got addressed:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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next prev parent reply other threads:[~2024-01-09 18:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-29 21:49 [v2 00/10] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2023-12-29 21:49 ` [v2 01/10] RISC-V: Fix the typo in Scountovf CSR name Atish Patra
2023-12-29 21:49 ` [v2 02/10] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2023-12-29 21:49 ` [v2 03/10] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2023-12-30 7:55 ` Anup Patel
2024-01-09 18:24 ` Conor Dooley
2023-12-29 21:49 ` [v2 04/10] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2023-12-29 21:49 ` [v2 05/10] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2023-12-30 7:58 ` Anup Patel
2024-01-09 18:30 ` Conor Dooley [this message]
2023-12-29 21:49 ` [v2 06/10] RISC-V: KVM: No need to update the counter value during reset Atish Patra
2023-12-30 8:00 ` Anup Patel
2023-12-29 21:49 ` [v2 07/10] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra
2023-12-30 8:01 ` Anup Patel
2023-12-29 21:49 ` [v2 08/10] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2023-12-30 8:05 ` Anup Patel
2023-12-29 21:49 ` [v2 09/10] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2023-12-30 8:09 ` Anup Patel
2024-01-10 12:38 ` Vladimir Isaev
2024-01-10 15:23 ` Atish Kumar Patra
2023-12-29 21:49 ` [v2 10/10] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2023-12-30 8:10 ` Anup Patel
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