[kvmtool PATCH 00/10] More ISA extensions

[kvmtool PATCH 00/10] More ISA extensions

[Anup Patel]

This series adds support more ISA extensions namely: Zbc, scalar crypto,
vector crypto, Zfh[min], Zihintntl, Zvfh[min], and Zfa. The series also
adds a command-line option to disable SBI STA extension for Guest/VM.

These patches can also be found in the riscv_more_exts_v1 branch at:
https://github.com/avpatel/kvmtool.git

Anup Patel (10):
  Sync-up header with Linux-6.8-rc4 for KVM RISC-V
  kvmtool: Fix absence of __packed definition
  riscv: Add Zbc extension support
  riscv: Add scalar crypto extensions support
  riscv: Add vector crypto extensions support
  riscv: Add Zfh[min] extensions support
  riscv: Add Zihintntl extension support
  riscv: Add Zvfh[min] extensions support
  riscv: Add Zfa extensiona support
  riscv: Allow disabling SBI STA extension for Guest

 include/kvm/compiler.h              |   2 +
 include/linux/kvm.h                 | 140 ++++++++++------------------
 include/linux/virtio_config.h       |   8 +-
 include/linux/virtio_pci.h          |  68 ++++++++++++++
 riscv/fdt.c                         |  27 ++++++
 riscv/include/asm/kvm.h             |  40 ++++++++
 riscv/include/kvm/csr.h             |  15 +++
 riscv/include/kvm/kvm-config-arch.h |  86 ++++++++++++++++-
 riscv/kvm-cpu.c                     |  31 ++++++
 x86/include/asm/kvm.h               |   3 +
 10 files changed, 328 insertions(+), 92 deletions(-)
 create mode 100644 riscv/include/kvm/csr.h

-- 
2.34.1

[kvmtool PATCH 01/10] Sync-up header with Linux-6.8-rc4 for KVM RISC-V

[Anup Patel]

We sync-up Linux headers to get latest KVM RISC-V headers having
Zbc, Scalar crypto, Vector crypto, Zfh[min], Zihintntl, Zvfh[min],
Zfa, and SBI steal-time support.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 include/linux/kvm.h           | 140 ++++++++++++----------------------
 include/linux/virtio_config.h |   8 +-
 include/linux/virtio_pci.h    |  68 +++++++++++++++++
 riscv/include/asm/kvm.h       |  40 ++++++++++
 x86/include/asm/kvm.h         |   3 +
 5 files changed, 168 insertions(+), 91 deletions(-)

diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 211b86d..c330853 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -16,76 +16,6 @@
 
 #define KVM_API_VERSION 12
 
-/* *** Deprecated interfaces *** */
-
-#define KVM_TRC_SHIFT           16
-
-#define KVM_TRC_ENTRYEXIT       (1 << KVM_TRC_SHIFT)
-#define KVM_TRC_HANDLER         (1 << (KVM_TRC_SHIFT + 1))
-
-#define KVM_TRC_VMENTRY         (KVM_TRC_ENTRYEXIT + 0x01)
-#define KVM_TRC_VMEXIT          (KVM_TRC_ENTRYEXIT + 0x02)
-#define KVM_TRC_PAGE_FAULT      (KVM_TRC_HANDLER + 0x01)
-
-#define KVM_TRC_HEAD_SIZE       12
-#define KVM_TRC_CYCLE_SIZE      8
-#define KVM_TRC_EXTRA_MAX       7
-
-#define KVM_TRC_INJ_VIRQ         (KVM_TRC_HANDLER + 0x02)
-#define KVM_TRC_REDELIVER_EVT    (KVM_TRC_HANDLER + 0x03)
-#define KVM_TRC_PEND_INTR        (KVM_TRC_HANDLER + 0x04)
-#define KVM_TRC_IO_READ          (KVM_TRC_HANDLER + 0x05)
-#define KVM_TRC_IO_WRITE         (KVM_TRC_HANDLER + 0x06)
-#define KVM_TRC_CR_READ          (KVM_TRC_HANDLER + 0x07)
-#define KVM_TRC_CR_WRITE         (KVM_TRC_HANDLER + 0x08)
-#define KVM_TRC_DR_READ          (KVM_TRC_HANDLER + 0x09)
-#define KVM_TRC_DR_WRITE         (KVM_TRC_HANDLER + 0x0A)
-#define KVM_TRC_MSR_READ         (KVM_TRC_HANDLER + 0x0B)
-#define KVM_TRC_MSR_WRITE        (KVM_TRC_HANDLER + 0x0C)
-#define KVM_TRC_CPUID            (KVM_TRC_HANDLER + 0x0D)
-#define KVM_TRC_INTR             (KVM_TRC_HANDLER + 0x0E)
-#define KVM_TRC_NMI              (KVM_TRC_HANDLER + 0x0F)
-#define KVM_TRC_VMMCALL          (KVM_TRC_HANDLER + 0x10)
-#define KVM_TRC_HLT              (KVM_TRC_HANDLER + 0x11)
-#define KVM_TRC_CLTS             (KVM_TRC_HANDLER + 0x12)
-#define KVM_TRC_LMSW             (KVM_TRC_HANDLER + 0x13)
-#define KVM_TRC_APIC_ACCESS      (KVM_TRC_HANDLER + 0x14)
-#define KVM_TRC_TDP_FAULT        (KVM_TRC_HANDLER + 0x15)
-#define KVM_TRC_GTLB_WRITE       (KVM_TRC_HANDLER + 0x16)
-#define KVM_TRC_STLB_WRITE       (KVM_TRC_HANDLER + 0x17)
-#define KVM_TRC_STLB_INVAL       (KVM_TRC_HANDLER + 0x18)
-#define KVM_TRC_PPC_INSTR        (KVM_TRC_HANDLER + 0x19)
-
-struct kvm_user_trace_setup {
-	__u32 buf_size;
-	__u32 buf_nr;
-};
-
-#define __KVM_DEPRECATED_MAIN_W_0x06 \
-	_IOW(KVMIO, 0x06, struct kvm_user_trace_setup)
-#define __KVM_DEPRECATED_MAIN_0x07 _IO(KVMIO, 0x07)
-#define __KVM_DEPRECATED_MAIN_0x08 _IO(KVMIO, 0x08)
-
-#define __KVM_DEPRECATED_VM_R_0x70 _IOR(KVMIO, 0x70, struct kvm_assigned_irq)
-
-struct kvm_breakpoint {
-	__u32 enabled;
-	__u32 padding;
-	__u64 address;
-};
-
-struct kvm_debug_guest {
-	__u32 enabled;
-	__u32 pad;
-	struct kvm_breakpoint breakpoints[4];
-	__u32 singlestep;
-};
-
-#define __KVM_DEPRECATED_VCPU_W_0x87 _IOW(KVMIO, 0x87, struct kvm_debug_guest)
-
-/* *** End of deprecated interfaces *** */
-
-
 /* for KVM_SET_USER_MEMORY_REGION */
 struct kvm_userspace_memory_region {
 	__u32 slot;
@@ -95,6 +25,19 @@ struct kvm_userspace_memory_region {
 	__u64 userspace_addr; /* start of the userspace allocated memory */
 };
 
+/* for KVM_SET_USER_MEMORY_REGION2 */
+struct kvm_userspace_memory_region2 {
+	__u32 slot;
+	__u32 flags;
+	__u64 guest_phys_addr;
+	__u64 memory_size;
+	__u64 userspace_addr;
+	__u64 guest_memfd_offset;
+	__u32 guest_memfd;
+	__u32 pad1;
+	__u64 pad2[14];
+};
+
 /*
  * The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
  * userspace, other bits are reserved for kvm internal use which are defined
@@ -102,6 +45,7 @@ struct kvm_userspace_memory_region {
  */
 #define KVM_MEM_LOG_DIRTY_PAGES	(1UL << 0)
 #define KVM_MEM_READONLY	(1UL << 1)
+#define KVM_MEM_GUEST_MEMFD	(1UL << 2)
 
 /* for KVM_IRQ_LINE */
 struct kvm_irq_level {
@@ -265,6 +209,7 @@ struct kvm_xen_exit {
 #define KVM_EXIT_RISCV_CSR        36
 #define KVM_EXIT_NOTIFY           37
 #define KVM_EXIT_LOONGARCH_IOCSR  38
+#define KVM_EXIT_MEMORY_FAULT     39
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -518,6 +463,13 @@ struct kvm_run {
 #define KVM_NOTIFY_CONTEXT_INVALID	(1 << 0)
 			__u32 flags;
 		} notify;
+		/* KVM_EXIT_MEMORY_FAULT */
+		struct {
+#define KVM_MEMORY_EXIT_FLAG_PRIVATE	(1ULL << 3)
+			__u64 flags;
+			__u64 gpa;
+			__u64 size;
+		} memory_fault;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
@@ -945,9 +897,6 @@ struct kvm_ppc_resize_hpt {
  */
 #define KVM_GET_VCPU_MMAP_SIZE    _IO(KVMIO,   0x04) /* in bytes */
 #define KVM_GET_SUPPORTED_CPUID   _IOWR(KVMIO, 0x05, struct kvm_cpuid2)
-#define KVM_TRACE_ENABLE          __KVM_DEPRECATED_MAIN_W_0x06
-#define KVM_TRACE_PAUSE           __KVM_DEPRECATED_MAIN_0x07
-#define KVM_TRACE_DISABLE         __KVM_DEPRECATED_MAIN_0x08
 #define KVM_GET_EMULATED_CPUID	  _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
 #define KVM_GET_MSR_FEATURE_INDEX_LIST    _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
 
@@ -1201,6 +1150,11 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
 #define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
 #define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
+#define KVM_CAP_USER_MEMORY2 231
+#define KVM_CAP_MEMORY_FAULT_INFO 232
+#define KVM_CAP_MEMORY_ATTRIBUTES 233
+#define KVM_CAP_GUEST_MEMFD 234
+#define KVM_CAP_VM_TYPES 235
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
@@ -1291,6 +1245,7 @@ struct kvm_x86_mce {
 #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL	(1 << 4)
 #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND		(1 << 5)
 #define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG	(1 << 6)
+#define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE	(1 << 7)
 
 struct kvm_xen_hvm_config {
 	__u32 flags;
@@ -1483,6 +1438,8 @@ struct kvm_vfio_spapr_tce {
 					struct kvm_userspace_memory_region)
 #define KVM_SET_TSS_ADDR          _IO(KVMIO,   0x47)
 #define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO,  0x48, __u64)
+#define KVM_SET_USER_MEMORY_REGION2 _IOW(KVMIO, 0x49, \
+					 struct kvm_userspace_memory_region2)
 
 /* enable ucontrol for s390 */
 struct kvm_s390_ucas_mapping {
@@ -1507,20 +1464,8 @@ struct kvm_s390_ucas_mapping {
 			_IOW(KVMIO,  0x67, struct kvm_coalesced_mmio_zone)
 #define KVM_UNREGISTER_COALESCED_MMIO \
 			_IOW(KVMIO,  0x68, struct kvm_coalesced_mmio_zone)
-#define KVM_ASSIGN_PCI_DEVICE     _IOR(KVMIO,  0x69, \
-				       struct kvm_assigned_pci_dev)
 #define KVM_SET_GSI_ROUTING       _IOW(KVMIO,  0x6a, struct kvm_irq_routing)
-/* deprecated, replaced by KVM_ASSIGN_DEV_IRQ */
-#define KVM_ASSIGN_IRQ            __KVM_DEPRECATED_VM_R_0x70
-#define KVM_ASSIGN_DEV_IRQ        _IOW(KVMIO,  0x70, struct kvm_assigned_irq)
 #define KVM_REINJECT_CONTROL      _IO(KVMIO,   0x71)
-#define KVM_DEASSIGN_PCI_DEVICE   _IOW(KVMIO,  0x72, \
-				       struct kvm_assigned_pci_dev)
-#define KVM_ASSIGN_SET_MSIX_NR    _IOW(KVMIO,  0x73, \
-				       struct kvm_assigned_msix_nr)
-#define KVM_ASSIGN_SET_MSIX_ENTRY _IOW(KVMIO,  0x74, \
-				       struct kvm_assigned_msix_entry)
-#define KVM_DEASSIGN_DEV_IRQ      _IOW(KVMIO,  0x75, struct kvm_assigned_irq)
 #define KVM_IRQFD                 _IOW(KVMIO,  0x76, struct kvm_irqfd)
 #define KVM_CREATE_PIT2		  _IOW(KVMIO,  0x77, struct kvm_pit_config)
 #define KVM_SET_BOOT_CPU_ID       _IO(KVMIO,   0x78)
@@ -1537,9 +1482,6 @@ struct kvm_s390_ucas_mapping {
 *  KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */
 #define KVM_SET_TSC_KHZ           _IO(KVMIO,  0xa2)
 #define KVM_GET_TSC_KHZ           _IO(KVMIO,  0xa3)
-/* Available with KVM_CAP_PCI_2_3 */
-#define KVM_ASSIGN_SET_INTX_MASK  _IOW(KVMIO,  0xa4, \
-				       struct kvm_assigned_pci_dev)
 /* Available with KVM_CAP_SIGNAL_MSI */
 #define KVM_SIGNAL_MSI            _IOW(KVMIO,  0xa5, struct kvm_msi)
 /* Available with KVM_CAP_PPC_GET_SMMU_INFO */
@@ -1592,8 +1534,6 @@ struct kvm_s390_ucas_mapping {
 #define KVM_SET_SREGS             _IOW(KVMIO,  0x84, struct kvm_sregs)
 #define KVM_TRANSLATE             _IOWR(KVMIO, 0x85, struct kvm_translation)
 #define KVM_INTERRUPT             _IOW(KVMIO,  0x86, struct kvm_interrupt)
-/* KVM_DEBUG_GUEST is no longer supported, use KVM_SET_GUEST_DEBUG instead */
-#define KVM_DEBUG_GUEST           __KVM_DEPRECATED_VCPU_W_0x87
 #define KVM_GET_MSRS              _IOWR(KVMIO, 0x88, struct kvm_msrs)
 #define KVM_SET_MSRS              _IOW(KVMIO,  0x89, struct kvm_msrs)
 #define KVM_SET_CPUID             _IOW(KVMIO,  0x8a, struct kvm_cpuid)
@@ -2267,4 +2207,24 @@ struct kvm_s390_zpci_op {
 /* flags for kvm_s390_zpci_op->u.reg_aen.flags */
 #define KVM_S390_ZPCIOP_REGAEN_HOST    (1 << 0)
 
+/* Available with KVM_CAP_MEMORY_ATTRIBUTES */
+#define KVM_SET_MEMORY_ATTRIBUTES              _IOW(KVMIO,  0xd2, struct kvm_memory_attributes)
+
+struct kvm_memory_attributes {
+	__u64 address;
+	__u64 size;
+	__u64 attributes;
+	__u64 flags;
+};
+
+#define KVM_MEMORY_ATTRIBUTE_PRIVATE           (1ULL << 3)
+
+#define KVM_CREATE_GUEST_MEMFD	_IOWR(KVMIO,  0xd4, struct kvm_create_guest_memfd)
+
+struct kvm_create_guest_memfd {
+	__u64 size;
+	__u64 flags;
+	__u64 reserved[6];
+};
+
 #endif /* __LINUX_KVM_H */
diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h
index 8881aea..2445f36 100644
--- a/include/linux/virtio_config.h
+++ b/include/linux/virtio_config.h
@@ -52,7 +52,7 @@
  * rest are per-device feature bits.
  */
 #define VIRTIO_TRANSPORT_F_START	28
-#define VIRTIO_TRANSPORT_F_END		41
+#define VIRTIO_TRANSPORT_F_END		42
 
 #ifndef VIRTIO_CONFIG_NO_LEGACY
 /* Do we get callbacks when the ring is completely used, even if we've
@@ -114,4 +114,10 @@
  * This feature indicates that the driver can reset a queue individually.
  */
 #define VIRTIO_F_RING_RESET		40
+
+/*
+ * This feature indicates that the device support administration virtqueues.
+ */
+#define VIRTIO_F_ADMIN_VQ		41
+
 #endif /* _UAPI_LINUX_VIRTIO_CONFIG_H */
diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h
index 44f4dd2..ef3810d 100644
--- a/include/linux/virtio_pci.h
+++ b/include/linux/virtio_pci.h
@@ -175,6 +175,9 @@ struct virtio_pci_modern_common_cfg {
 
 	__le16 queue_notify_data;	/* read-write */
 	__le16 queue_reset;		/* read-write */
+
+	__le16 admin_queue_index;	/* read-only */
+	__le16 admin_queue_num;		/* read-only */
 };
 
 /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
@@ -215,7 +218,72 @@ struct virtio_pci_cfg_cap {
 #define VIRTIO_PCI_COMMON_Q_USEDHI	52
 #define VIRTIO_PCI_COMMON_Q_NDATA	56
 #define VIRTIO_PCI_COMMON_Q_RESET	58
+#define VIRTIO_PCI_COMMON_ADM_Q_IDX	60
+#define VIRTIO_PCI_COMMON_ADM_Q_NUM	62
 
 #endif /* VIRTIO_PCI_NO_MODERN */
 
+/* Admin command status. */
+#define VIRTIO_ADMIN_STATUS_OK		0
+
+/* Admin command opcode. */
+#define VIRTIO_ADMIN_CMD_LIST_QUERY	0x0
+#define VIRTIO_ADMIN_CMD_LIST_USE	0x1
+
+/* Admin command group type. */
+#define VIRTIO_ADMIN_GROUP_TYPE_SRIOV	0x1
+
+/* Transitional device admin command. */
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE	0x2
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ		0x3
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE		0x4
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ		0x5
+#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO		0x6
+
+struct __packed virtio_admin_cmd_hdr {
+	__le16 opcode;
+	/*
+	 * 1 - SR-IOV
+	 * 2-65535 - reserved
+	 */
+	__le16 group_type;
+	/* Unused, reserved for future extensions. */
+	__u8 reserved1[12];
+	__le64 group_member_id;
+};
+
+struct __packed virtio_admin_cmd_status {
+	__le16 status;
+	__le16 status_qualifier;
+	/* Unused, reserved for future extensions. */
+	__u8 reserved2[4];
+};
+
+struct __packed virtio_admin_cmd_legacy_wr_data {
+	__u8 offset; /* Starting offset of the register(s) to write. */
+	__u8 reserved[7];
+	__u8 registers[];
+};
+
+struct __packed virtio_admin_cmd_legacy_rd_data {
+	__u8 offset; /* Starting offset of the register(s) to read. */
+};
+
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
+
+#define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
+
+struct __packed virtio_admin_cmd_notify_info_data {
+	__u8 flags; /* 0 = end of list, 1 = owner device, 2 = member device */
+	__u8 bar; /* BAR of the member or the owner device */
+	__u8 padding[6];
+	__le64 offset; /* Offset within bar. */
+};
+
+struct virtio_admin_cmd_notify_info_result {
+	struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
+};
+
 #endif
diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h
index 60d3b21..7499e88 100644
--- a/riscv/include/asm/kvm.h
+++ b/riscv/include/asm/kvm.h
@@ -139,6 +139,33 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZIHPM,
 	KVM_RISCV_ISA_EXT_SMSTATEEN,
 	KVM_RISCV_ISA_EXT_ZICOND,
+	KVM_RISCV_ISA_EXT_ZBC,
+	KVM_RISCV_ISA_EXT_ZBKB,
+	KVM_RISCV_ISA_EXT_ZBKC,
+	KVM_RISCV_ISA_EXT_ZBKX,
+	KVM_RISCV_ISA_EXT_ZKND,
+	KVM_RISCV_ISA_EXT_ZKNE,
+	KVM_RISCV_ISA_EXT_ZKNH,
+	KVM_RISCV_ISA_EXT_ZKR,
+	KVM_RISCV_ISA_EXT_ZKSED,
+	KVM_RISCV_ISA_EXT_ZKSH,
+	KVM_RISCV_ISA_EXT_ZKT,
+	KVM_RISCV_ISA_EXT_ZVBB,
+	KVM_RISCV_ISA_EXT_ZVBC,
+	KVM_RISCV_ISA_EXT_ZVKB,
+	KVM_RISCV_ISA_EXT_ZVKG,
+	KVM_RISCV_ISA_EXT_ZVKNED,
+	KVM_RISCV_ISA_EXT_ZVKNHA,
+	KVM_RISCV_ISA_EXT_ZVKNHB,
+	KVM_RISCV_ISA_EXT_ZVKSED,
+	KVM_RISCV_ISA_EXT_ZVKSH,
+	KVM_RISCV_ISA_EXT_ZVKT,
+	KVM_RISCV_ISA_EXT_ZFH,
+	KVM_RISCV_ISA_EXT_ZFHMIN,
+	KVM_RISCV_ISA_EXT_ZIHINTNTL,
+	KVM_RISCV_ISA_EXT_ZVFH,
+	KVM_RISCV_ISA_EXT_ZVFHMIN,
+	KVM_RISCV_ISA_EXT_ZFA,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
@@ -157,9 +184,16 @@ enum KVM_RISCV_SBI_EXT_ID {
 	KVM_RISCV_SBI_EXT_EXPERIMENTAL,
 	KVM_RISCV_SBI_EXT_VENDOR,
 	KVM_RISCV_SBI_EXT_DBCN,
+	KVM_RISCV_SBI_EXT_STA,
 	KVM_RISCV_SBI_EXT_MAX,
 };
 
+/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_sbi_sta {
+	unsigned long shmem_lo;
+	unsigned long shmem_hi;
+};
+
 /* Possible states for kvm_riscv_timer */
 #define KVM_RISCV_TIMER_STATE_OFF	0
 #define KVM_RISCV_TIMER_STATE_ON	1
@@ -241,6 +275,12 @@ enum KVM_RISCV_SBI_EXT_ID {
 #define KVM_REG_RISCV_VECTOR_REG(n)	\
 		((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
 
+/* Registers for specific SBI extensions are mapped as type 10 */
+#define KVM_REG_RISCV_SBI_STATE		(0x0a << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_STA		(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_STA_REG(name)		\
+		(offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
+
 /* Device Control API: RISC-V AIA */
 #define KVM_DEV_RISCV_APLIC_ALIGN		0x1000
 #define KVM_DEV_RISCV_APLIC_SIZE		0x4000
diff --git a/x86/include/asm/kvm.h b/x86/include/asm/kvm.h
index 1a6a1f9..a448d09 100644
--- a/x86/include/asm/kvm.h
+++ b/x86/include/asm/kvm.h
@@ -562,4 +562,7 @@ struct kvm_pmu_event_filter {
 /* x86-specific KVM_EXIT_HYPERCALL flags. */
 #define KVM_EXIT_HYPERCALL_LONG_MODE	BIT(0)
 
+#define KVM_X86_DEFAULT_VM	0
+#define KVM_X86_SW_PROTECTED_VM	1
+
 #endif /* _ASM_X86_KVM_H */
-- 
2.34.1

[kvmtool PATCH 02/10] kvmtool: Fix absence of __packed definition

[Anup Patel]

The absence of __packed definition in kvm/compiler.h cause build
failer after syncing kernel headers with Linux-6.8 because the
kernel header uapi/linux/virtio_pci.h uses __packed for structures.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 include/kvm/compiler.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/kvm/compiler.h b/include/kvm/compiler.h
index 2013a83..dd8a22a 100644
--- a/include/kvm/compiler.h
+++ b/include/kvm/compiler.h
@@ -1,6 +1,8 @@
 #ifndef KVM_COMPILER_H_
 #define KVM_COMPILER_H_
 
+#include <linux/compiler.h>
+
 #ifndef __compiletime_error
 # define __compiletime_error(message)
 #endif
-- 
2.34.1

[kvmtool PATCH 03/10] riscv: Add Zbc extension support

[Anup Patel]

When the Zbc extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 1 +
 riscv/include/kvm/kvm-config-arch.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 8485acf..84b6087 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -24,6 +24,7 @@ struct isa_ext_info isa_info_arr[] = {
 	{"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
 	{"zba", KVM_RISCV_ISA_EXT_ZBA},
 	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
+	{"zbc", KVM_RISCV_ISA_EXT_ZBC},
 	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index d2fc2d4..6d09eee 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -49,6 +49,9 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zbb",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBB],	\
 		    "Disable Zbb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbc",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBC],	\
+		    "Disable Zbc Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zbs",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
 		    "Disable Zbs Extension"),				\
-- 
2.34.1

[kvmtool PATCH 04/10] riscv: Add scalar crypto extensions support

[Anup Patel]

When the scalar extensions are available expose them to the guest
via device tree so that guest can use it. This includes extensions
Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt.

The Zkr extension requires SEED CSR emulation in user space so
we also add related KVM_EXIT_RISCV_CSR handling.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 10 ++++++++++
 riscv/include/kvm/csr.h             | 15 ++++++++++++++
 riscv/include/kvm/kvm-config-arch.h | 30 ++++++++++++++++++++++++++++
 riscv/kvm-cpu.c                     | 31 +++++++++++++++++++++++++++++
 4 files changed, 86 insertions(+)
 create mode 100644 riscv/include/kvm/csr.h

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 84b6087..be87e9a 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -25,6 +25,9 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zba", KVM_RISCV_ISA_EXT_ZBA},
 	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
 	{"zbc", KVM_RISCV_ISA_EXT_ZBC},
+	{"zbkb", KVM_RISCV_ISA_EXT_ZBKB},
+	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
+	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
 	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
@@ -34,6 +37,13 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
 	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
+	{"zknd", KVM_RISCV_ISA_EXT_ZKND},
+	{"zkne", KVM_RISCV_ISA_EXT_ZKNE},
+	{"zknh", KVM_RISCV_ISA_EXT_ZKNH},
+	{"zkr", KVM_RISCV_ISA_EXT_ZKR},
+	{"zksed", KVM_RISCV_ISA_EXT_ZKSED},
+	{"zksh", KVM_RISCV_ISA_EXT_ZKSH},
+	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
 };
 
 static void dump_fdt(const char *dtb_file, void *fdt)
diff --git a/riscv/include/kvm/csr.h b/riscv/include/kvm/csr.h
new file mode 100644
index 0000000..2d27f74
--- /dev/null
+++ b/riscv/include/kvm/csr.h
@@ -0,0 +1,15 @@
+#ifndef KVM__KVM_CSR_H
+#define KVM__KVM_CSR_H
+
+#include <linux/const.h>
+
+/* Scalar Crypto Extension - Entropy */
+#define CSR_SEED		0x015
+#define SEED_OPST_MASK		_AC(0xC0000000, UL)
+#define SEED_OPST_BIST		_AC(0x00000000, UL)
+#define SEED_OPST_WAIT		_AC(0x40000000, UL)
+#define SEED_OPST_ES16		_AC(0x80000000, UL)
+#define SEED_OPST_DEAD		_AC(0xC0000000, UL)
+#define SEED_ENTROPY_MASK	_AC(0xFFFF, UL)
+
+#endif /* KVM__KVM_CSR_H */
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 6d09eee..3764d7c 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -52,6 +52,15 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zbc",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBC],	\
 		    "Disable Zbc Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbkb",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKB],	\
+		    "Disable Zbkb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbkc",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKC],	\
+		    "Disable Zbkc Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbkx",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKX],	\
+		    "Disable Zbkx Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zbs",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
 		    "Disable Zbs Extension"),				\
@@ -79,6 +88,27 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zihpm",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHPM],	\
 		    "Disable Zihpm Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zknd",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKND],	\
+		    "Disable Zknd Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zkne",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNE],	\
+		    "Disable Zkne Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zknh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNH],	\
+		    "Disable Zknh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zkr",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKR],	\
+		    "Disable Zkr Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zksed",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSED],	\
+		    "Disable Zksed Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zksh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSH],	\
+		    "Disable Zksh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zkt",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT],	\
+		    "Disable Zkt Extension"),				\
 	OPT_BOOLEAN('\0', "disable-sbi-legacy",				\
 		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],	\
 		    "Disable SBI Legacy Extensions"),			\
diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
index c4e83c4..3e17c12 100644
--- a/riscv/kvm-cpu.c
+++ b/riscv/kvm-cpu.c
@@ -1,3 +1,4 @@
+#include "kvm/csr.h"
 #include "kvm/kvm-cpu.h"
 #include "kvm/kvm.h"
 #include "kvm/virtio.h"
@@ -222,11 +223,41 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
 	return ret;
 }
 
+static bool kvm_cpu_riscv_csr(struct kvm_cpu *vcpu)
+{
+	int dfd = kvm_cpu__get_debug_fd();
+	bool ret = true;
+
+	switch (vcpu->kvm_run->riscv_csr.csr_num) {
+	case CSR_SEED:
+		/*
+		 * We ignore the new_value and write_mask and simply
+		 * return a random value as SEED.
+		 */
+		vcpu->kvm_run->riscv_csr.ret_value = rand() & SEED_ENTROPY_MASK;
+		break;
+	default:
+		dprintf(dfd, "Unhandled CSR access\n");
+		dprintf(dfd, "csr_num=0x%lx new_value=0x%lx\n",
+			vcpu->kvm_run->riscv_csr.csr_num,
+			vcpu->kvm_run->riscv_csr.new_value);
+		dprintf(dfd, "write_mask=0x%lx ret_value=0x%lx\n",
+			vcpu->kvm_run->riscv_csr.write_mask,
+			vcpu->kvm_run->riscv_csr.ret_value);
+		ret = false;
+		break;
+	};
+
+	return ret;
+}
+
 bool kvm_cpu__handle_exit(struct kvm_cpu *vcpu)
 {
 	switch (vcpu->kvm_run->exit_reason) {
 	case KVM_EXIT_RISCV_SBI:
 		return kvm_cpu_riscv_sbi(vcpu);
+	case KVM_EXIT_RISCV_CSR:
+		return kvm_cpu_riscv_csr(vcpu);
 	default:
 		break;
 	};
-- 
2.34.1

[kvmtool PATCH 05/10] riscv: Add vector crypto extensions support

[Anup Patel]

When the vector extensions are available expose them to the guest
via device tree so that guest can use it. This includes extensions
Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh,
and Zvkt.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 10 ++++++++++
 riscv/include/kvm/kvm-config-arch.h | 30 +++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index be87e9a..44058dc 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -44,6 +44,16 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zksed", KVM_RISCV_ISA_EXT_ZKSED},
 	{"zksh", KVM_RISCV_ISA_EXT_ZKSH},
 	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
+	{"zvbb", KVM_RISCV_ISA_EXT_ZVBB},
+	{"zvbc", KVM_RISCV_ISA_EXT_ZVBC},
+	{"zvkb", KVM_RISCV_ISA_EXT_ZVKB},
+	{"zvkg", KVM_RISCV_ISA_EXT_ZVKG},
+	{"zvkned", KVM_RISCV_ISA_EXT_ZVKNED},
+	{"zvknha", KVM_RISCV_ISA_EXT_ZVKNHA},
+	{"zvknhb", KVM_RISCV_ISA_EXT_ZVKNHB},
+	{"zvksed", KVM_RISCV_ISA_EXT_ZVKSED},
+	{"zvksh", KVM_RISCV_ISA_EXT_ZVKSH},
+	{"zvkt", KVM_RISCV_ISA_EXT_ZVKT},
 };
 
 static void dump_fdt(const char *dtb_file, void *fdt)
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 3764d7c..ae648ce 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -109,6 +109,36 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zkt",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT],	\
 		    "Disable Zkt Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvbb",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBB],	\
+		    "Disable Zvbb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvbc",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC],	\
+		    "Disable Zvbc Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvkb",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB],	\
+		    "Disable Zvkb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvkg",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKG],	\
+		    "Disable Zvkg Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvkned",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNED],	\
+		    "Disable Zvkned Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zvknha",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHA],	\
+		    "Disable Zvknha Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zvknhb",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHB],	\
+		    "Disable Zvknhb Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zvksed",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSED],	\
+		    "Disable Zvksed Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zvksh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSH],	\
+		    "Disable Zvksh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvkt",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKT],	\
+		    "Disable Zvkt Extension"),				\
 	OPT_BOOLEAN('\0', "disable-sbi-legacy",				\
 		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],	\
 		    "Disable SBI Legacy Extensions"),			\
-- 
2.34.1

[kvmtool PATCH 06/10] riscv: Add Zfh[min] extensions support

[Anup Patel]

When the Zfh[min] extensions are available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 44058dc..7687624 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -29,6 +29,8 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
 	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
 	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
+	{"zfh", KVM_RISCV_ISA_EXT_ZFH},
+	{"zfhmin", KVM_RISCV_ISA_EXT_ZFHMIN},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
 	{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index ae648ce..f1ac56b 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -64,6 +64,12 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zbs",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
 		    "Disable Zbs Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zfh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFH],	\
+		    "Disable Zfh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zfhmin",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFHMIN],	\
+		    "Disable Zfhmin Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zicbom",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM],	\
 		    "Disable Zicbom Extension"),			\
-- 
2.34.1

[kvmtool PATCH 07/10] riscv: Add Zihintntl extension support

[Anup Patel]

When the Zihintntl extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 1 +
 riscv/include/kvm/kvm-config-arch.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 7687624..80e045d 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -37,6 +37,7 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zicond", KVM_RISCV_ISA_EXT_ZICOND},
 	{"zicsr", KVM_RISCV_ISA_EXT_ZICSR},
 	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
+	{"zihintntl", KVM_RISCV_ISA_EXT_ZIHINTNTL},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
 	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
 	{"zknd", KVM_RISCV_ISA_EXT_ZKND},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index f1ac56b..2935c01 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -88,6 +88,9 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zifencei",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIFENCEI],	\
 		    "Disable Zifencei Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zihintntl",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTNTL],	\
+		    "Disable Zihintntl Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zihintpause",			\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\
 		    "Disable Zihintpause Extension"),			\
-- 
2.34.1

[kvmtool PATCH 08/10] riscv: Add Zvfh[min] extensions support

[Anup Patel]

When the Zvfh[min] extensions are available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 80e045d..005301e 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -49,6 +49,8 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
 	{"zvbb", KVM_RISCV_ISA_EXT_ZVBB},
 	{"zvbc", KVM_RISCV_ISA_EXT_ZVBC},
+	{"zvfh", KVM_RISCV_ISA_EXT_ZVFH},
+	{"zvfhmin", KVM_RISCV_ISA_EXT_ZVFHMIN},
 	{"zvkb", KVM_RISCV_ISA_EXT_ZVKB},
 	{"zvkg", KVM_RISCV_ISA_EXT_ZVKG},
 	{"zvkned", KVM_RISCV_ISA_EXT_ZVKNED},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 2935c01..10ca3b8 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -124,6 +124,12 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zvbc",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC],	\
 		    "Disable Zvbc Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvfh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFH],	\
+		    "Disable Zvfh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvfhmin",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFHMIN],	\
+		    "Disable Zvfhmin Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zvkb",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB],	\
 		    "Disable Zvkb Extension"),				\
-- 
2.34.1

[kvmtool PATCH 09/10] riscv: Add Zfa extensiona support

[Anup Patel]

When the Zfa extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 1 +
 riscv/include/kvm/kvm-config-arch.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 005301e..cc8070d 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -29,6 +29,7 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
 	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
 	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
+	{"zfa", KVM_RISCV_ISA_EXT_ZFA},
 	{"zfh", KVM_RISCV_ISA_EXT_ZFH},
 	{"zfhmin", KVM_RISCV_ISA_EXT_ZFHMIN},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 10ca3b8..6415d3d 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -64,6 +64,9 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zbs",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
 		    "Disable Zbs Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zfa",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFA],	\
+		    "Disable Zfa Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zfh",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFH],	\
 		    "Disable Zfh Extension"),				\
-- 
2.34.1

[kvmtool PATCH 10/10] riscv: Allow disabling SBI STA extension for Guest

[Anup Patel]

We add "--disable-sbi-sta" options to allow users disable SBI steal-time
extension for the Guest.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/include/kvm/kvm-config-arch.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 6415d3d..e562d71 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -186,6 +186,9 @@ struct kvm_config_arch {
 		    "Disable SBI Vendor Extensions"),			\
 	OPT_BOOLEAN('\0', "disable-sbi-dbcn",				\
 		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN],	\
-		    "Disable SBI DBCN Extension"),
+		    "Disable SBI DBCN Extension"),			\
+	OPT_BOOLEAN('\0', "disable-sbi-sta",				\
+		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_STA],	\
+		    "Disable SBI STA Extension"),
 
 #endif /* KVM__KVM_CONFIG_ARCH_H */
-- 
2.34.1

Re: [kvmtool PATCH 03/10] riscv: Add Zbc extension support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:34PM +0530, Anup Patel wrote:
> When the Zbc extension is available expose it to the guest
> via device tree so that guest can use it.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 1 +
>  riscv/include/kvm/kvm-config-arch.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 8485acf..84b6087 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -24,6 +24,7 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
>  	{"zba", KVM_RISCV_ISA_EXT_ZBA},
>  	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
> +	{"zbc", KVM_RISCV_ISA_EXT_ZBC},
>  	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
>  	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
>  	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index d2fc2d4..6d09eee 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -49,6 +49,9 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zbb",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBB],	\
>  		    "Disable Zbb Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zbc",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBC],	\
> +		    "Disable Zbc Extension"),				\
>  	OPT_BOOLEAN('\0', "disable-zbs",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
>  		    "Disable Zbs Extension"),				\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 04/10] riscv: Add scalar crypto extensions support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:35PM +0530, Anup Patel wrote:
> When the scalar extensions are available expose them to the guest
> via device tree so that guest can use it. This includes extensions
> Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt.
> 
> The Zkr extension requires SEED CSR emulation in user space so
> we also add related KVM_EXIT_RISCV_CSR handling.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 10 ++++++++++
>  riscv/include/kvm/csr.h             | 15 ++++++++++++++
>  riscv/include/kvm/kvm-config-arch.h | 30 ++++++++++++++++++++++++++++
>  riscv/kvm-cpu.c                     | 31 +++++++++++++++++++++++++++++
>  4 files changed, 86 insertions(+)
>  create mode 100644 riscv/include/kvm/csr.h
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 84b6087..be87e9a 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -25,6 +25,9 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zba", KVM_RISCV_ISA_EXT_ZBA},
>  	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
>  	{"zbc", KVM_RISCV_ISA_EXT_ZBC},
> +	{"zbkb", KVM_RISCV_ISA_EXT_ZBKB},
> +	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
> +	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
>  	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
>  	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
>  	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
> @@ -34,6 +37,13 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
>  	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
>  	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
> +	{"zknd", KVM_RISCV_ISA_EXT_ZKND},
> +	{"zkne", KVM_RISCV_ISA_EXT_ZKNE},
> +	{"zknh", KVM_RISCV_ISA_EXT_ZKNH},
> +	{"zkr", KVM_RISCV_ISA_EXT_ZKR},
> +	{"zksed", KVM_RISCV_ISA_EXT_ZKSED},
> +	{"zksh", KVM_RISCV_ISA_EXT_ZKSH},
> +	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
>  };
>  
>  static void dump_fdt(const char *dtb_file, void *fdt)
> diff --git a/riscv/include/kvm/csr.h b/riscv/include/kvm/csr.h
> new file mode 100644
> index 0000000..2d27f74
> --- /dev/null
> +++ b/riscv/include/kvm/csr.h
> @@ -0,0 +1,15 @@

SPDX header?

> +#ifndef KVM__KVM_CSR_H
> +#define KVM__KVM_CSR_H
> +
> +#include <linux/const.h>
> +
> +/* Scalar Crypto Extension - Entropy */
> +#define CSR_SEED		0x015
> +#define SEED_OPST_MASK		_AC(0xC0000000, UL)
> +#define SEED_OPST_BIST		_AC(0x00000000, UL)
> +#define SEED_OPST_WAIT		_AC(0x40000000, UL)
> +#define SEED_OPST_ES16		_AC(0x80000000, UL)
> +#define SEED_OPST_DEAD		_AC(0xC0000000, UL)
> +#define SEED_ENTROPY_MASK	_AC(0xFFFF, UL)
> +
> +#endif /* KVM__KVM_CSR_H */
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index 6d09eee..3764d7c 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -52,6 +52,15 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zbc",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBC],	\
>  		    "Disable Zbc Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zbkb",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKB],	\
> +		    "Disable Zbkb Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zbkc",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKC],	\
> +		    "Disable Zbkc Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zbkx",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKX],	\
> +		    "Disable Zbkx Extension"),				\
>  	OPT_BOOLEAN('\0', "disable-zbs",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
>  		    "Disable Zbs Extension"),				\
> @@ -79,6 +88,27 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zihpm",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHPM],	\
>  		    "Disable Zihpm Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zknd",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKND],	\
> +		    "Disable Zknd Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zkne",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNE],	\
> +		    "Disable Zkne Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zknh",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNH],	\
> +		    "Disable Zknh Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zkr",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKR],	\
> +		    "Disable Zkr Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zksed",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSED],	\
> +		    "Disable Zksed Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zksh",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSH],	\
> +		    "Disable Zksh Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zkt",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT],	\
> +		    "Disable Zkt Extension"),				\
>  	OPT_BOOLEAN('\0', "disable-sbi-legacy",				\
>  		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],	\
>  		    "Disable SBI Legacy Extensions"),			\
> diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
> index c4e83c4..3e17c12 100644
> --- a/riscv/kvm-cpu.c
> +++ b/riscv/kvm-cpu.c
> @@ -1,3 +1,4 @@
> +#include "kvm/csr.h"
>  #include "kvm/kvm-cpu.h"
>  #include "kvm/kvm.h"
>  #include "kvm/virtio.h"
> @@ -222,11 +223,41 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
>  	return ret;
>  }
>  
> +static bool kvm_cpu_riscv_csr(struct kvm_cpu *vcpu)
> +{
> +	int dfd = kvm_cpu__get_debug_fd();
> +	bool ret = true;
> +
> +	switch (vcpu->kvm_run->riscv_csr.csr_num) {
> +	case CSR_SEED:
> +		/*
> +		 * We ignore the new_value and write_mask and simply
> +		 * return a random value as SEED.
> +		 */
> +		vcpu->kvm_run->riscv_csr.ret_value = rand() & SEED_ENTROPY_MASK;

Shouldn't this be

 vcpu->kvm_run->riscv_csr.ret_value = SEED_OPST_ES16 | (rand() & SEED_ENTROPY_MASK);

> +		break;
> +	default:
> +		dprintf(dfd, "Unhandled CSR access\n");
> +		dprintf(dfd, "csr_num=0x%lx new_value=0x%lx\n",
> +			vcpu->kvm_run->riscv_csr.csr_num,
> +			vcpu->kvm_run->riscv_csr.new_value);
> +		dprintf(dfd, "write_mask=0x%lx ret_value=0x%lx\n",
> +			vcpu->kvm_run->riscv_csr.write_mask,
> +			vcpu->kvm_run->riscv_csr.ret_value);
> +		ret = false;
> +		break;
> +	};

Extra ';'

> +
> +	return ret;
> +}
> +
>  bool kvm_cpu__handle_exit(struct kvm_cpu *vcpu)
>  {
>  	switch (vcpu->kvm_run->exit_reason) {
>  	case KVM_EXIT_RISCV_SBI:
>  		return kvm_cpu_riscv_sbi(vcpu);
> +	case KVM_EXIT_RISCV_CSR:
> +		return kvm_cpu_riscv_csr(vcpu);
>  	default:
>  		break;
>  	};
> -- 
> 2.34.1
>

Thanks,
drew

Re: [kvmtool PATCH 05/10] riscv: Add vector crypto extensions support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:36PM +0530, Anup Patel wrote:
> When the vector extensions are available expose them to the guest
> via device tree so that guest can use it. This includes extensions
> Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh,
> and Zvkt.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 10 ++++++++++
>  riscv/include/kvm/kvm-config-arch.h | 30 +++++++++++++++++++++++++++++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index be87e9a..44058dc 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -44,6 +44,16 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zksed", KVM_RISCV_ISA_EXT_ZKSED},
>  	{"zksh", KVM_RISCV_ISA_EXT_ZKSH},
>  	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
> +	{"zvbb", KVM_RISCV_ISA_EXT_ZVBB},
> +	{"zvbc", KVM_RISCV_ISA_EXT_ZVBC},
> +	{"zvkb", KVM_RISCV_ISA_EXT_ZVKB},
> +	{"zvkg", KVM_RISCV_ISA_EXT_ZVKG},
> +	{"zvkned", KVM_RISCV_ISA_EXT_ZVKNED},
> +	{"zvknha", KVM_RISCV_ISA_EXT_ZVKNHA},
> +	{"zvknhb", KVM_RISCV_ISA_EXT_ZVKNHB},
> +	{"zvksed", KVM_RISCV_ISA_EXT_ZVKSED},
> +	{"zvksh", KVM_RISCV_ISA_EXT_ZVKSH},
> +	{"zvkt", KVM_RISCV_ISA_EXT_ZVKT},
>  };
>  
>  static void dump_fdt(const char *dtb_file, void *fdt)
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index 3764d7c..ae648ce 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -109,6 +109,36 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zkt",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT],	\
>  		    "Disable Zkt Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvbb",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBB],	\
> +		    "Disable Zvbb Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvbc",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC],	\
> +		    "Disable Zvbc Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvkb",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB],	\
> +		    "Disable Zvkb Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvkg",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKG],	\
> +		    "Disable Zvkg Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvkned",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNED],	\
> +		    "Disable Zvkned Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-zvknha",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHA],	\
> +		    "Disable Zvknha Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-zvknhb",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHB],	\
> +		    "Disable Zvknhb Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-zvksed",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSED],	\
> +		    "Disable Zvksed Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-zvksh",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSH],	\
> +		    "Disable Zvksh Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvkt",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKT],	\
> +		    "Disable Zvkt Extension"),				\
>  	OPT_BOOLEAN('\0', "disable-sbi-legacy",				\
>  		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],	\
>  		    "Disable SBI Legacy Extensions"),			\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 06/10] riscv: Add Zfh[min] extensions support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:37PM +0530, Anup Patel wrote:
> When the Zfh[min] extensions are available expose it to the guest
> via device tree so that guest can use it.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 2 ++
>  riscv/include/kvm/kvm-config-arch.h | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 44058dc..7687624 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -29,6 +29,8 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
>  	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
>  	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
> +	{"zfh", KVM_RISCV_ISA_EXT_ZFH},
> +	{"zfhmin", KVM_RISCV_ISA_EXT_ZFHMIN},
>  	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
>  	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
>  	{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index ae648ce..f1ac56b 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -64,6 +64,12 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zbs",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
>  		    "Disable Zbs Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zfh",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFH],	\
> +		    "Disable Zfh Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zfhmin",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFHMIN],	\
> +		    "Disable Zfhmin Extension"),			\
>  	OPT_BOOLEAN('\0', "disable-zicbom",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM],	\
>  		    "Disable Zicbom Extension"),			\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 07/10] riscv: Add Zihintntl extension support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:38PM +0530, Anup Patel wrote:
> When the Zihintntl extension is available expose it to the guest
> via device tree so that guest can use it.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 1 +
>  riscv/include/kvm/kvm-config-arch.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 7687624..80e045d 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -37,6 +37,7 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zicond", KVM_RISCV_ISA_EXT_ZICOND},
>  	{"zicsr", KVM_RISCV_ISA_EXT_ZICSR},
>  	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
> +	{"zihintntl", KVM_RISCV_ISA_EXT_ZIHINTNTL},
>  	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
>  	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
>  	{"zknd", KVM_RISCV_ISA_EXT_ZKND},
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index f1ac56b..2935c01 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -88,6 +88,9 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zifencei",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIFENCEI],	\
>  		    "Disable Zifencei Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-zihintntl",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTNTL],	\
> +		    "Disable Zihintntl Extension"),			\
>  	OPT_BOOLEAN('\0', "disable-zihintpause",			\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\
>  		    "Disable Zihintpause Extension"),			\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 08/10] riscv: Add Zvfh[min] extensions support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:39PM +0530, Anup Patel wrote:
> When the Zvfh[min] extensions are available expose it to the guest
> via device tree so that guest can use it.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 2 ++
>  riscv/include/kvm/kvm-config-arch.h | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 80e045d..005301e 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -49,6 +49,8 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
>  	{"zvbb", KVM_RISCV_ISA_EXT_ZVBB},
>  	{"zvbc", KVM_RISCV_ISA_EXT_ZVBC},
> +	{"zvfh", KVM_RISCV_ISA_EXT_ZVFH},
> +	{"zvfhmin", KVM_RISCV_ISA_EXT_ZVFHMIN},
>  	{"zvkb", KVM_RISCV_ISA_EXT_ZVKB},
>  	{"zvkg", KVM_RISCV_ISA_EXT_ZVKG},
>  	{"zvkned", KVM_RISCV_ISA_EXT_ZVKNED},
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index 2935c01..10ca3b8 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -124,6 +124,12 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zvbc",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC],	\
>  		    "Disable Zvbc Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvfh",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFH],	\
> +		    "Disable Zvfh Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zvfhmin",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFHMIN],	\
> +		    "Disable Zvfhmin Extension"),			\
>  	OPT_BOOLEAN('\0', "disable-zvkb",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB],	\
>  		    "Disable Zvkb Extension"),				\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 09/10] riscv: Add Zfa extensiona support

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:40PM +0530, Anup Patel wrote:
> When the Zfa extension is available expose it to the guest
> via device tree so that guest can use it.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/fdt.c                         | 1 +
>  riscv/include/kvm/kvm-config-arch.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/riscv/fdt.c b/riscv/fdt.c
> index 005301e..cc8070d 100644
> --- a/riscv/fdt.c
> +++ b/riscv/fdt.c
> @@ -29,6 +29,7 @@ struct isa_ext_info isa_info_arr[] = {
>  	{"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
>  	{"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
>  	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
> +	{"zfa", KVM_RISCV_ISA_EXT_ZFA},
>  	{"zfh", KVM_RISCV_ISA_EXT_ZFH},
>  	{"zfhmin", KVM_RISCV_ISA_EXT_ZFHMIN},
>  	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index 10ca3b8..6415d3d 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -64,6 +64,9 @@ struct kvm_config_arch {
>  	OPT_BOOLEAN('\0', "disable-zbs",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
>  		    "Disable Zbs Extension"),				\
> +	OPT_BOOLEAN('\0', "disable-zfa",				\
> +		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFA],	\
> +		    "Disable Zfa Extension"),				\
>  	OPT_BOOLEAN('\0', "disable-zfh",				\
>  		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZFH],	\
>  		    "Disable Zfh Extension"),				\
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 10/10] riscv: Allow disabling SBI STA extension for Guest

[Andrew Jones]

On Wed, Feb 14, 2024 at 05:51:41PM +0530, Anup Patel wrote:
> We add "--disable-sbi-sta" options to allow users disable SBI steal-time
> extension for the Guest.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  riscv/include/kvm/kvm-config-arch.h | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> index 6415d3d..e562d71 100644
> --- a/riscv/include/kvm/kvm-config-arch.h
> +++ b/riscv/include/kvm/kvm-config-arch.h
> @@ -186,6 +186,9 @@ struct kvm_config_arch {
>  		    "Disable SBI Vendor Extensions"),			\
>  	OPT_BOOLEAN('\0', "disable-sbi-dbcn",				\
>  		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN],	\
> -		    "Disable SBI DBCN Extension"),
> +		    "Disable SBI DBCN Extension"),			\
> +	OPT_BOOLEAN('\0', "disable-sbi-sta",				\
> +		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_STA],	\
> +		    "Disable SBI STA Extension"),
>  
>  #endif /* KVM__KVM_CONFIG_ARCH_H */
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [kvmtool PATCH 04/10] riscv: Add scalar crypto extensions support

[Anup Patel]

On Tue, Mar 5, 2024 at 7:18 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Wed, Feb 14, 2024 at 05:51:35PM +0530, Anup Patel wrote:
> > When the scalar extensions are available expose them to the guest
> > via device tree so that guest can use it. This includes extensions
> > Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt.
> >
> > The Zkr extension requires SEED CSR emulation in user space so
> > we also add related KVM_EXIT_RISCV_CSR handling.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> >  riscv/fdt.c                         | 10 ++++++++++
> >  riscv/include/kvm/csr.h             | 15 ++++++++++++++
> >  riscv/include/kvm/kvm-config-arch.h | 30 ++++++++++++++++++++++++++++
> >  riscv/kvm-cpu.c                     | 31 +++++++++++++++++++++++++++++
> >  4 files changed, 86 insertions(+)
> >  create mode 100644 riscv/include/kvm/csr.h
> >
> > diff --git a/riscv/fdt.c b/riscv/fdt.c
> > index 84b6087..be87e9a 100644
> > --- a/riscv/fdt.c
> > +++ b/riscv/fdt.c
> > @@ -25,6 +25,9 @@ struct isa_ext_info isa_info_arr[] = {
> >       {"zba", KVM_RISCV_ISA_EXT_ZBA},
> >       {"zbb", KVM_RISCV_ISA_EXT_ZBB},
> >       {"zbc", KVM_RISCV_ISA_EXT_ZBC},
> > +     {"zbkb", KVM_RISCV_ISA_EXT_ZBKB},
> > +     {"zbkc", KVM_RISCV_ISA_EXT_ZBKC},
> > +     {"zbkx", KVM_RISCV_ISA_EXT_ZBKX},
> >       {"zbs", KVM_RISCV_ISA_EXT_ZBS},
> >       {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
> >       {"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
> > @@ -34,6 +37,13 @@ struct isa_ext_info isa_info_arr[] = {
> >       {"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
> >       {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
> >       {"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
> > +     {"zknd", KVM_RISCV_ISA_EXT_ZKND},
> > +     {"zkne", KVM_RISCV_ISA_EXT_ZKNE},
> > +     {"zknh", KVM_RISCV_ISA_EXT_ZKNH},
> > +     {"zkr", KVM_RISCV_ISA_EXT_ZKR},
> > +     {"zksed", KVM_RISCV_ISA_EXT_ZKSED},
> > +     {"zksh", KVM_RISCV_ISA_EXT_ZKSH},
> > +     {"zkt", KVM_RISCV_ISA_EXT_ZKT},
> >  };
> >
> >  static void dump_fdt(const char *dtb_file, void *fdt)
> > diff --git a/riscv/include/kvm/csr.h b/riscv/include/kvm/csr.h
> > new file mode 100644
> > index 0000000..2d27f74
> > --- /dev/null
> > +++ b/riscv/include/kvm/csr.h
> > @@ -0,0 +1,15 @@
>
> SPDX header?

Added in v2.

>
> > +#ifndef KVM__KVM_CSR_H
> > +#define KVM__KVM_CSR_H
> > +
> > +#include <linux/const.h>
> > +
> > +/* Scalar Crypto Extension - Entropy */
> > +#define CSR_SEED             0x015
> > +#define SEED_OPST_MASK               _AC(0xC0000000, UL)
> > +#define SEED_OPST_BIST               _AC(0x00000000, UL)
> > +#define SEED_OPST_WAIT               _AC(0x40000000, UL)
> > +#define SEED_OPST_ES16               _AC(0x80000000, UL)
> > +#define SEED_OPST_DEAD               _AC(0xC0000000, UL)
> > +#define SEED_ENTROPY_MASK    _AC(0xFFFF, UL)
> > +
> > +#endif /* KVM__KVM_CSR_H */
> > diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
> > index 6d09eee..3764d7c 100644
> > --- a/riscv/include/kvm/kvm-config-arch.h
> > +++ b/riscv/include/kvm/kvm-config-arch.h
> > @@ -52,6 +52,15 @@ struct kvm_config_arch {
> >       OPT_BOOLEAN('\0', "disable-zbc",                                \
> >                   &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBC],        \
> >                   "Disable Zbc Extension"),                           \
> > +     OPT_BOOLEAN('\0', "disable-zbkb",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKB],       \
> > +                 "Disable Zbkb Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zbkc",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKC],       \
> > +                 "Disable Zbkc Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zbkx",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBKX],       \
> > +                 "Disable Zbkx Extension"),                          \
> >       OPT_BOOLEAN('\0', "disable-zbs",                                \
> >                   &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],        \
> >                   "Disable Zbs Extension"),                           \
> > @@ -79,6 +88,27 @@ struct kvm_config_arch {
> >       OPT_BOOLEAN('\0', "disable-zihpm",                              \
> >                   &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHPM],      \
> >                   "Disable Zihpm Extension"),                         \
> > +     OPT_BOOLEAN('\0', "disable-zknd",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKND],       \
> > +                 "Disable Zknd Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zkne",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNE],       \
> > +                 "Disable Zkne Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zknh",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKNH],       \
> > +                 "Disable Zknh Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zkr",                                \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKR],        \
> > +                 "Disable Zkr Extension"),                           \
> > +     OPT_BOOLEAN('\0', "disable-zksed",                              \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSED],      \
> > +                 "Disable Zksed Extension"),                         \
> > +     OPT_BOOLEAN('\0', "disable-zksh",                               \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKSH],       \
> > +                 "Disable Zksh Extension"),                          \
> > +     OPT_BOOLEAN('\0', "disable-zkt",                                \
> > +                 &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT],        \
> > +                 "Disable Zkt Extension"),                           \
> >       OPT_BOOLEAN('\0', "disable-sbi-legacy",                         \
> >                   &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],    \
> >                   "Disable SBI Legacy Extensions"),                   \
> > diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
> > index c4e83c4..3e17c12 100644
> > --- a/riscv/kvm-cpu.c
> > +++ b/riscv/kvm-cpu.c
> > @@ -1,3 +1,4 @@
> > +#include "kvm/csr.h"
> >  #include "kvm/kvm-cpu.h"
> >  #include "kvm/kvm.h"
> >  #include "kvm/virtio.h"
> > @@ -222,11 +223,41 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
> >       return ret;
> >  }
> >
> > +static bool kvm_cpu_riscv_csr(struct kvm_cpu *vcpu)
> > +{
> > +     int dfd = kvm_cpu__get_debug_fd();
> > +     bool ret = true;
> > +
> > +     switch (vcpu->kvm_run->riscv_csr.csr_num) {
> > +     case CSR_SEED:
> > +             /*
> > +              * We ignore the new_value and write_mask and simply
> > +              * return a random value as SEED.
> > +              */
> > +             vcpu->kvm_run->riscv_csr.ret_value = rand() & SEED_ENTROPY_MASK;
>
> Shouldn't this be
>
>  vcpu->kvm_run->riscv_csr.ret_value = SEED_OPST_ES16 | (rand() & SEED_ENTROPY_MASK);

Good catch. Addressed in v2.

>
> > +             break;
> > +     default:
> > +             dprintf(dfd, "Unhandled CSR access\n");
> > +             dprintf(dfd, "csr_num=0x%lx new_value=0x%lx\n",
> > +                     vcpu->kvm_run->riscv_csr.csr_num,
> > +                     vcpu->kvm_run->riscv_csr.new_value);
> > +             dprintf(dfd, "write_mask=0x%lx ret_value=0x%lx\n",
> > +                     vcpu->kvm_run->riscv_csr.write_mask,
> > +                     vcpu->kvm_run->riscv_csr.ret_value);
> > +             ret = false;
> > +             break;
> > +     };
>
> Extra ';'

Updated in v2.

>
> > +
> > +     return ret;
> > +}
> > +
> >  bool kvm_cpu__handle_exit(struct kvm_cpu *vcpu)
> >  {
> >       switch (vcpu->kvm_run->exit_reason) {
> >       case KVM_EXIT_RISCV_SBI:
> >               return kvm_cpu_riscv_sbi(vcpu);
> > +     case KVM_EXIT_RISCV_CSR:
> > +             return kvm_cpu_riscv_csr(vcpu);
> >       default:
> >               break;
> >       };
> > --
> > 2.34.1
> >
>
> Thanks,
> drew

Regards,
Anup