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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id l33-20020a05600c1d2100b00412ca88537dsm3348026wms.0.2024.03.01.23.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 23:47:39 -0800 (PST) Date: Sat, 2 Mar 2024 08:47:33 +0100 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Anup Patel , Albert Ou , Alexandre Ghiti , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: Re: [PATCH v4 06/15] RISC-V: KVM: No need to update the counter value during reset Message-ID: <20240302-a82f4ba5d90bc3d85f3ed83b@orel> References: <20240229010130.1380926-1-atishp@rivosinc.com> <20240229010130.1380926-7-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240229010130.1380926-7-atishp@rivosinc.com> On Wed, Feb 28, 2024 at 05:01:21PM -0800, Atish Patra wrote: > The virtual counter value is updated during pmu_ctr_read. There is no need > to update it in reset case. Otherwise, it will be counted twice which is > incorrect. > > Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/kvm/vcpu_pmu.c | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c > index 86391a5061dd..b1574c043f77 100644 > --- a/arch/riscv/kvm/vcpu_pmu.c > +++ b/arch/riscv/kvm/vcpu_pmu.c > @@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, > { > struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); > int i, pmc_index, sbiret = 0; > - u64 enabled, running; > struct kvm_pmc *pmc; > int fevent_code; > > @@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, > sbiret = SBI_ERR_ALREADY_STOPPED; > } > > - if (flags & SBI_PMU_STOP_FLAG_RESET) { > - /* Relase the counter if this is a reset request */ > - pmc->counter_val += perf_event_read_value(pmc->perf_event, > - &enabled, &running); > + if (flags & SBI_PMU_STOP_FLAG_RESET) > + /* Release the counter if this is a reset request */ > kvm_pmu_release_perf_event(pmc); > - } > } else { > sbiret = SBI_ERR_INVALID_PARAM; > } > -- > 2.34.1 > Reviewed-by: Andrew Jones