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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id v23-20020a170906565700b00a455ff77e7bsm2054317ejr.88.2024.03.05.05.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Mar 2024 05:49:29 -0800 (PST) Date: Tue, 5 Mar 2024 14:49:28 +0100 From: Andrew Jones To: Anup Patel Cc: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org, Paolo Bonzini , Atish Patra , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: Re: [kvmtool PATCH 05/10] riscv: Add vector crypto extensions support Message-ID: <20240305-c8b0107a805e1edca5fbe797@orel> References: <20240214122141.305126-1-apatel@ventanamicro.com> <20240214122141.305126-6-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240214122141.305126-6-apatel@ventanamicro.com> On Wed, Feb 14, 2024 at 05:51:36PM +0530, Anup Patel wrote: > When the vector extensions are available expose them to the guest > via device tree so that guest can use it. This includes extensions > Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, > and Zvkt. > > Signed-off-by: Anup Patel > --- > riscv/fdt.c | 10 ++++++++++ > riscv/include/kvm/kvm-config-arch.h | 30 +++++++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/riscv/fdt.c b/riscv/fdt.c > index be87e9a..44058dc 100644 > --- a/riscv/fdt.c > +++ b/riscv/fdt.c > @@ -44,6 +44,16 @@ struct isa_ext_info isa_info_arr[] = { > {"zksed", KVM_RISCV_ISA_EXT_ZKSED}, > {"zksh", KVM_RISCV_ISA_EXT_ZKSH}, > {"zkt", KVM_RISCV_ISA_EXT_ZKT}, > + {"zvbb", KVM_RISCV_ISA_EXT_ZVBB}, > + {"zvbc", KVM_RISCV_ISA_EXT_ZVBC}, > + {"zvkb", KVM_RISCV_ISA_EXT_ZVKB}, > + {"zvkg", KVM_RISCV_ISA_EXT_ZVKG}, > + {"zvkned", KVM_RISCV_ISA_EXT_ZVKNED}, > + {"zvknha", KVM_RISCV_ISA_EXT_ZVKNHA}, > + {"zvknhb", KVM_RISCV_ISA_EXT_ZVKNHB}, > + {"zvksed", KVM_RISCV_ISA_EXT_ZVKSED}, > + {"zvksh", KVM_RISCV_ISA_EXT_ZVKSH}, > + {"zvkt", KVM_RISCV_ISA_EXT_ZVKT}, > }; > > static void dump_fdt(const char *dtb_file, void *fdt) > diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h > index 3764d7c..ae648ce 100644 > --- a/riscv/include/kvm/kvm-config-arch.h > +++ b/riscv/include/kvm/kvm-config-arch.h > @@ -109,6 +109,36 @@ struct kvm_config_arch { > OPT_BOOLEAN('\0', "disable-zkt", \ > &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZKT], \ > "Disable Zkt Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvbb", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBB], \ > + "Disable Zvbb Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvbc", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC], \ > + "Disable Zvbc Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvkb", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB], \ > + "Disable Zvkb Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvkg", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKG], \ > + "Disable Zvkg Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvkned", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNED], \ > + "Disable Zvkned Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvknha", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHA], \ > + "Disable Zvknha Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvknhb", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKNHB], \ > + "Disable Zvknhb Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvksed", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSED], \ > + "Disable Zvksed Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvksh", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKSH], \ > + "Disable Zvksh Extension"), \ > + OPT_BOOLEAN('\0', "disable-zvkt", \ > + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKT], \ > + "Disable Zvkt Extension"), \ > OPT_BOOLEAN('\0', "disable-sbi-legacy", \ > &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01], \ > "Disable SBI Legacy Extensions"), \ > -- > 2.34.1 > Reviewed-by: Andrew Jones