From: Pavan Kumar Paluri <papaluri@amd.com>
To: <kvm@vger.kernel.org>
Cc: <andrew.jones@linux.dev>, <pbonzini@redhat.com>,
<thomas.lendacky@amd.com>, <michael.roth@amd.com>,
Pavan Kumar Paluri <papaluri@amd.com>
Subject: [kvm-unit-tests PATCH v3 3/4] x86 AMD SEV-ES: Set GHCB page attributes for a new page table
Date: Thu, 28 Mar 2024 10:21:11 -0500 [thread overview]
Message-ID: <20240328152112.800177-3-papaluri@amd.com> (raw)
In-Reply-To: <20240328152112.800177-1-papaluri@amd.com>
SEV-ES/SNP guest uses GHCB page to communicate with the host. Such a
page should remain unencrypted (its c-bit should be unset). Therefore,
call setup_ghcb_pte() in the path of setup_vm() to make sure c-bit of
GHCB's pte is unset, for a new page table that will be setup as a part
of page allocation for SEV-ES/SNP tests later on.
Signed-off-by: Pavan Kumar Paluri <papaluri@amd.com>
---
lib/x86/vm.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/x86/vm.c b/lib/x86/vm.c
index 90f73fbb2dfd..ce2063aee75d 100644
--- a/lib/x86/vm.c
+++ b/lib/x86/vm.c
@@ -3,6 +3,7 @@
#include "vmalloc.h"
#include "alloc_page.h"
#include "smp.h"
+#include "amd_sev.h"
static pteval_t pte_opt_mask;
@@ -197,6 +198,11 @@ void *setup_mmu(phys_addr_t end_of_memory, void *opt_mask)
init_alloc_vpage((void*)(3ul << 30));
#endif
+#ifdef CONFIG_EFI
+ if (amd_sev_es_enabled())
+ setup_ghcb_pte(cr3);
+#endif
+
write_cr3(virt_to_phys(cr3));
#ifndef __x86_64__
write_cr4(X86_CR4_PSE);
--
2.34.1
next prev parent reply other threads:[~2024-03-28 15:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-28 15:21 [kvm-unit-tests PATCH v3 1/4] x86 EFI: Bypass call to fdt_check_header() Pavan Kumar Paluri
2024-03-28 15:21 ` [kvm-unit-tests PATCH v3 2/4] x86/efi: Retry call to efi exit boot services Pavan Kumar Paluri
2024-03-28 16:33 ` Andrew Jones
2024-03-28 21:48 ` Paluri, PavanKumar
2024-03-28 15:21 ` Pavan Kumar Paluri [this message]
2024-03-28 15:21 ` [kvm-unit-tests PATCH v3 4/4] x86 AMD SEV-ES: Setup a new page table and install level-1 PTEs Pavan Kumar Paluri
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