Re: [PATCH 06/15] x86/irq: Set up per host CPU posted interrupt descriptors

Jacob Pan
2024-02-13T19:39:30Z

On Fri, 26 Jan 2024 15:42:28 -0800, Jacob Pan
<jacob.jun.pan@linux.intel.com> wrote:
I have made a couple of mistakes here, caught by LKP testing.
Reported by Oliver Sang.

>
> +#ifdef CONFIG_X86_POSTED_MSI
> +
> +/* Posted Interrupt Descriptors for coalesced MSIs to be posted */
> +DEFINE_PER_CPU_ALIGNED(struct pi_desc, posted_interrupt_desc);
> +
> +void intel_posted_msi_init(void)
> +{
> + struct pi_desc *pid = this_cpu_ptr(&posted_interrupt_desc);
> +
> + pid->nv = POSTED_MSI_NOTIFICATION_VECTOR;
> + pid->ndst = this_cpu_read(x86_cpu_to_apicid);
Based on VT-d specification 9.11, middle portion of the 32 bit field
are used in xAPIC mode instead of the lowest 8 bit. Not sure why it was
designed this way, making sure people ready the spec carefully :)

xAPIC Mode (Physical):
319:304 - Reserved (0)
303:296 - APIC DestinationID[7:0]
295:288 - Reserved (0)
x2APIC Mode (Physical):
319:288 - APIC DestinationID[31:0]

So it should be something like:
pid->ndst = x2apic_enabled() ? apic_id : apic_id << 8;

> +}
> +}
partitioning mistake, will fix.

> +#endif /* X86_POSTED_MSI */

Thanks,

Jacob