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Received: from j130084.upc-j.chello.nl ([24.132.130.84] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4H21-0000000Cv4t-3aA5; Tue, 07 May 2024 09:22:42 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 797333006AB; Tue, 7 May 2024 11:22:41 +0200 (CEST) Date: Tue, 7 May 2024 11:22:41 +0200 From: Peter Zijlstra To: Mingwei Zhang Cc: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler Message-ID: <20240507092241.GV40213@noisy.programming.kicks-ass.net> References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-13-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240506053020.3911940-13-mizhang@google.com> On Mon, May 06, 2024 at 05:29:37AM +0000, Mingwei Zhang wrote: > From: Xiong Zhang > > Add x86 specific function to switch PMI handler since passthrough PMU and host > PMU use different interrupt vectors. > > x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, > and guest LVTPC_MASK value should be reflected onto HW to indicate whether > guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. > > x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. > > Signed-off-by: Xiong Zhang > Signed-off-by: Dapeng Mi > --- > arch/x86/events/core.c | 17 +++++++++++++++++ > arch/x86/include/asm/perf_event.h | 3 +++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 09050641ce5d..8167f2230d3a 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) > } > EXPORT_SYMBOL_GPL(perf_guest_get_msrs); > > +void x86_perf_guest_enter(u32 guest_lvtpc) > +{ > + lockdep_assert_irqs_disabled(); > + > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | > + (guest_lvtpc & APIC_LVT_MASKED)); > +} > +EXPORT_SYMBOL_GPL(x86_perf_guest_enter); > + > +void x86_perf_guest_exit(void) > +{ > + lockdep_assert_irqs_disabled(); > + > + apic_write(APIC_LVTPC, APIC_DM_NMI); > +} > +EXPORT_SYMBOL_GPL(x86_perf_guest_exit); Urgghh... because it makes sense for this bare APIC write to be exported ?!? Can't this at the very least be hard tied to perf_guest_{enter,exit}() ?