From: "Clément Léger" <cleger@rivosinc.com>
To: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Anup Patel <anup@brainfault.org>, Shuah Khan <shuah@kernel.org>
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Atish Patra" <atishp@atishpatra.org>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: [PATCH v5 08/16] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb
Date: Fri, 17 May 2024 16:52:48 +0200 [thread overview]
Message-ID: <20240517145302.971019-9-cleger@rivosinc.com> (raw)
In-Reply-To: <20240517145302.971019-1-cleger@rivosinc.com>
The Zc* standard extension for code reduction introduces new extensions.
This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp
are left out of this patch since they are targeting microcontrollers/
embedded CPUs instead of application processors.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 3 ++
arch/riscv/include/asm/hwcap.h | 4 +++
arch/riscv/kernel/cpufeature.c | 44 ++++++++++++++++++++++++++++-
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 1a148cd67e0e..8611e1c8ec2d 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -46,6 +46,9 @@ void riscv_user_isa_enable(void);
#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL)
+#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \
+ _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate)
+
/* Used to declare pure "lasso" extension (Zk for instance) */
#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b1896dade74c..a5836fa6b998 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -81,6 +81,10 @@
#define RISCV_ISA_EXT_ZTSO 72
#define RISCV_ISA_EXT_ZACAS 73
#define RISCV_ISA_EXT_ZIMOP 74
+#define RISCV_ISA_EXT_ZCA 75
+#define RISCV_ISA_EXT_ZCB 76
+#define RISCV_ISA_EXT_ZCD 77
+#define RISCV_ISA_EXT_ZCF 78
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fa4ad73b770a..3bb2ef52a38b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -103,6 +103,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
return 0;
}
+static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+ return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER;
+}
+static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+ return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
+ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER;
+}
+
+static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+#ifdef CONFIG_64BIT
+ return -EINVAL;
+#else
+ return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
+ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f) ? 0 : -EPROBE_DEFER;
+#endif
+}
+
static const unsigned int riscv_zk_bundled_exts[] = {
RISCV_ISA_EXT_ZBKB,
RISCV_ISA_EXT_ZBKC,
@@ -183,6 +206,21 @@ static const unsigned int riscv_xlinuxenvcfg_exts[] = {
RISCV_ISA_EXT_XLINUXENVCFG
};
+/*
+ * Zc* spec states that:
+ * - C always implies Zca
+ * - C+F implies Zcf (RV32 only)
+ * - C+D implies Zcd
+ *
+ * These extensions will be enabled and then validated depending on the
+ * availability of F/D RV32.
+ */
+static const unsigned int riscv_c_exts[] = {
+ RISCV_ISA_EXT_ZCA,
+ RISCV_ISA_EXT_ZCF,
+ RISCV_ISA_EXT_ZCD,
+};
+
/*
* The canonical order of ISA extension names in the ISA string is defined in
* chapter 27 of the unprivileged specification.
@@ -229,7 +267,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
- __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
+ __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
@@ -248,6 +286,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
+ __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
+ __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
+ __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
+ __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
--
2.43.0
next prev parent reply other threads:[~2024-05-17 14:53 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-17 14:52 [PATCH v5 00/16] Add support for a few Zc* extensions, Zcmop and Zimop Clément Léger
2024-05-17 14:52 ` [PATCH v5 01/16] dt-bindings: riscv: add Zimop ISA extension description Clément Léger
2024-05-29 22:10 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 02/16] riscv: add ISA extension parsing for Zimop Clément Léger
2024-05-29 22:08 ` Charlie Jenkins
2024-05-29 22:21 ` Charlie Jenkins
2024-05-30 8:12 ` Clément Léger
2024-05-30 14:37 ` Charlie Jenkins
2024-05-30 14:38 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 03/16] riscv: hwprobe: export Zimop ISA extension Clément Léger
2024-05-29 22:11 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 04/16] RISC-V: KVM: Allow Zimop extension for Guest/VM Clément Léger
2024-05-17 15:17 ` Anup Patel
2024-05-29 22:16 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 05/16] KVM: riscv: selftests: Add Zimop extension to get-reg-list test Clément Léger
2024-05-17 15:18 ` Anup Patel
2024-05-17 14:52 ` [PATCH v5 06/16] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description Clément Léger
2024-05-29 22:13 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 07/16] riscv: add ISA extensions validation callback Clément Léger
2024-05-17 16:44 ` Conor Dooley
2024-05-21 7:58 ` Clément Léger
2024-05-17 14:52 ` Clément Léger [this message]
2024-05-21 19:49 ` [PATCH v5 08/16] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb Conor Dooley
2024-05-22 7:20 ` Clément Léger
2024-05-30 21:13 ` Palmer Dabbelt
2024-06-04 7:18 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 09/16] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Clément Léger
2024-05-30 15:25 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 10/16] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM Clément Léger
2024-05-17 14:52 ` [PATCH v5 11/16] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test Clément Léger
2024-05-17 14:52 ` [PATCH v5 12/16] dt-bindings: riscv: add Zcmop ISA extension description Clément Léger
2024-05-17 14:52 ` [PATCH v5 13/16] riscv: add ISA extension parsing for Zcmop Clément Léger
2024-05-30 15:48 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 14/16] riscv: hwprobe: export Zcmop ISA extension Clément Léger
2024-05-17 14:52 ` [PATCH v5 15/16] RISC-V: KVM: Allow Zcmop extension for Guest/VM Clément Léger
2024-05-17 14:52 ` [PATCH v5 16/16] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test Clément Léger
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