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From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	 kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	apatel@ventanamicro.com, alex@ghiti.fr,  greentime.hu@sifive.com,
	vincent.chen@sifive.com, Anup Patel <anup@brainfault.org>,
	 Atish Patra <atishp@atishpatra.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	 Shuah Khan <shuah@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
Date: Fri, 21 Jun 2024 10:53:31 +0200	[thread overview]
Message-ID: <20240621-f02c058395f929dfac9f3883@orel> (raw)
In-Reply-To: <20240605121512.32083-5-yongxuan.wang@sifive.com>

On Wed, Jun 05, 2024 at 08:15:10PM GMT, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svade and Svadu Extensions are
> available for guest OS.
> 
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
>  tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 222198dd6d04..1d32351ad55e 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg)
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
> +	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
> +	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
>  	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
> @@ -411,6 +413,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
>  		KVM_ISA_EXT_ARR(SSAIA),
>  		KVM_ISA_EXT_ARR(SSCOFPMF),
>  		KVM_ISA_EXT_ARR(SSTC),
> +		KVM_ISA_EXT_ARR(SVADE),
> +		KVM_ISA_EXT_ARR(SVADU),
>  		KVM_ISA_EXT_ARR(SVINVAL),
>  		KVM_ISA_EXT_ARR(SVNAPOT),
>  		KVM_ISA_EXT_ARR(SVPBMT),
> @@ -935,6 +939,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
>  KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
>  KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
>  KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
> +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
> +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
>  KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
>  KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
>  KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
> @@ -991,6 +997,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
>  	&config_smstateen,
>  	&config_sscofpmf,
>  	&config_sstc,
> +	&config_svade,
> +	&config_svadu,
>  	&config_svinval,
>  	&config_svnapot,
>  	&config_svpbmt,
> -- 
> 2.17.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

      reply	other threads:[~2024-06-21  8:53 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-05 12:15 [PATCH v5 0/4] Add Svade and Svadu Extensions Support Yong-Xuan Wang
2024-06-05 12:15 ` [PATCH v5 1/4] RISC-V: " Yong-Xuan Wang
2024-06-21  7:52   ` Alexandre Ghiti
2024-06-21  8:01     ` Conor Dooley
2024-06-21  8:06       ` Alexandre Ghiti
2024-06-21  8:43   ` Andrew Jones
2024-06-21 10:24     ` Conor Dooley
2024-06-21 10:31       ` Alexandre Ghiti
2024-06-21 10:42       ` Andrew Jones
2024-06-21 11:00         ` Conor Dooley
2024-06-21 12:06           ` Andrew Jones
2024-06-25 10:37             ` Yong-Xuan Wang
2024-06-05 12:15 ` [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
2024-06-05 16:54   ` Conor Dooley
2024-06-18 10:38     ` Yong-Xuan Wang
2024-06-19 18:11       ` Conor Dooley
2024-06-20  6:25     ` Anup Patel
2024-06-21  8:33       ` Andrew Jones
2024-06-21 10:11         ` Conor Dooley
2024-06-25 10:15         ` Yong-Xuan Wang
2024-06-21  8:37       ` Alexandre Ghiti
2024-06-21 10:17         ` Conor Dooley
2024-06-21 12:42           ` Alexandre Ghiti
2024-06-21 13:15             ` Andrew Jones
2024-06-21 14:04               ` Conor Dooley
2024-06-21 14:52                 ` Andrew Jones
2024-06-21 14:58                   ` Conor Dooley
2024-06-21 15:08                     ` Andrew Jones
2024-06-22 12:01                       ` Conor Dooley
2024-06-25 10:17                         ` Yong-Xuan Wang
2024-06-25 10:19                         ` Andrew Jones
2024-06-21  7:56   ` Alexandre Ghiti
2024-06-05 12:15 ` [PATCH v5 3/4] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Yong-Xuan Wang
2024-06-21  8:52   ` Andrew Jones
2024-06-05 12:15 ` [PATCH v5 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Yong-Xuan Wang
2024-06-21  8:53   ` Andrew Jones [this message]

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