* [kvmtool PATCH v3 1/4] Sync-up headers with Linux-6.10 kernel
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
@ 2024-08-21 14:26 ` Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 2/4] riscv: Add Sscofpmf extensiona support Anup Patel
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2024-08-21 14:26 UTC (permalink / raw)
To: Will Deacon, julien.thierry.kdev, maz
Cc: Paolo Bonzini, Atish Patra, Andrew Jones, Anup Patel, kvm,
kvm-riscv, Anup Patel
We sync-up Linux headers to get latest KVM RISC-V headers having
Sscofpmf support.
Signed-off-by: Anup Patel Anup Patel <apatel@ventanamicro.com>
---
include/linux/kvm.h | 4 +-
include/linux/virtio_net.h | 143 +++++++++++++++++++++++++++++++++++++
riscv/include/asm/kvm.h | 1 +
x86/include/asm/kvm.h | 22 +++++-
4 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 2190adb..d03842a 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -1221,9 +1221,9 @@ struct kvm_vfio_spapr_tce {
/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
-/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
+/* Available with KVM_CAP_PPC_MMU_RADIX or KVM_CAP_PPC_MMU_HASH_V3 */
#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
-/* Available with KVM_CAP_PPC_RADIX_MMU */
+/* Available with KVM_CAP_PPC_MMU_RADIX */
#define KVM_PPC_GET_RMMU_INFO _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
/* Available with KVM_CAP_PPC_GET_CPU_CHAR */
#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h
index cc65ef0..ac91747 100644
--- a/include/linux/virtio_net.h
+++ b/include/linux/virtio_net.h
@@ -56,6 +56,7 @@
#define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow
* Steering */
#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
+#define VIRTIO_NET_F_DEVICE_STATS 50 /* Device can provide device-level statistics. */
#define VIRTIO_NET_F_VQ_NOTF_COAL 52 /* Device supports virtqueue notification coalescing */
#define VIRTIO_NET_F_NOTF_COAL 53 /* Device supports notifications coalescing */
#define VIRTIO_NET_F_GUEST_USO4 54 /* Guest can handle USOv4 in. */
@@ -406,4 +407,146 @@ struct virtio_net_ctrl_coal_vq {
struct virtio_net_ctrl_coal coal;
};
+/*
+ * Device Statistics
+ */
+#define VIRTIO_NET_CTRL_STATS 8
+#define VIRTIO_NET_CTRL_STATS_QUERY 0
+#define VIRTIO_NET_CTRL_STATS_GET 1
+
+struct virtio_net_stats_capabilities {
+
+#define VIRTIO_NET_STATS_TYPE_CVQ (1ULL << 32)
+
+#define VIRTIO_NET_STATS_TYPE_RX_BASIC (1ULL << 0)
+#define VIRTIO_NET_STATS_TYPE_RX_CSUM (1ULL << 1)
+#define VIRTIO_NET_STATS_TYPE_RX_GSO (1ULL << 2)
+#define VIRTIO_NET_STATS_TYPE_RX_SPEED (1ULL << 3)
+
+#define VIRTIO_NET_STATS_TYPE_TX_BASIC (1ULL << 16)
+#define VIRTIO_NET_STATS_TYPE_TX_CSUM (1ULL << 17)
+#define VIRTIO_NET_STATS_TYPE_TX_GSO (1ULL << 18)
+#define VIRTIO_NET_STATS_TYPE_TX_SPEED (1ULL << 19)
+
+ __le64 supported_stats_types[1];
+};
+
+struct virtio_net_ctrl_queue_stats {
+ struct {
+ __le16 vq_index;
+ __le16 reserved[3];
+ __le64 types_bitmap[1];
+ } stats[1];
+};
+
+struct virtio_net_stats_reply_hdr {
+#define VIRTIO_NET_STATS_TYPE_REPLY_CVQ 32
+
+#define VIRTIO_NET_STATS_TYPE_REPLY_RX_BASIC 0
+#define VIRTIO_NET_STATS_TYPE_REPLY_RX_CSUM 1
+#define VIRTIO_NET_STATS_TYPE_REPLY_RX_GSO 2
+#define VIRTIO_NET_STATS_TYPE_REPLY_RX_SPEED 3
+
+#define VIRTIO_NET_STATS_TYPE_REPLY_TX_BASIC 16
+#define VIRTIO_NET_STATS_TYPE_REPLY_TX_CSUM 17
+#define VIRTIO_NET_STATS_TYPE_REPLY_TX_GSO 18
+#define VIRTIO_NET_STATS_TYPE_REPLY_TX_SPEED 19
+ __u8 type;
+ __u8 reserved;
+ __le16 vq_index;
+ __le16 reserved1;
+ __le16 size;
+};
+
+struct virtio_net_stats_cvq {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 command_num;
+ __le64 ok_num;
+};
+
+struct virtio_net_stats_rx_basic {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 rx_notifications;
+
+ __le64 rx_packets;
+ __le64 rx_bytes;
+
+ __le64 rx_interrupts;
+
+ __le64 rx_drops;
+ __le64 rx_drop_overruns;
+};
+
+struct virtio_net_stats_tx_basic {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 tx_notifications;
+
+ __le64 tx_packets;
+ __le64 tx_bytes;
+
+ __le64 tx_interrupts;
+
+ __le64 tx_drops;
+ __le64 tx_drop_malformed;
+};
+
+struct virtio_net_stats_rx_csum {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 rx_csum_valid;
+ __le64 rx_needs_csum;
+ __le64 rx_csum_none;
+ __le64 rx_csum_bad;
+};
+
+struct virtio_net_stats_tx_csum {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 tx_csum_none;
+ __le64 tx_needs_csum;
+};
+
+struct virtio_net_stats_rx_gso {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 rx_gso_packets;
+ __le64 rx_gso_bytes;
+ __le64 rx_gso_packets_coalesced;
+ __le64 rx_gso_bytes_coalesced;
+};
+
+struct virtio_net_stats_tx_gso {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ __le64 tx_gso_packets;
+ __le64 tx_gso_bytes;
+ __le64 tx_gso_segments;
+ __le64 tx_gso_segments_bytes;
+ __le64 tx_gso_packets_noseg;
+ __le64 tx_gso_bytes_noseg;
+};
+
+struct virtio_net_stats_rx_speed {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ /* rx_{packets,bytes}_allowance_exceeded are too long. So rename to
+ * short name.
+ */
+ __le64 rx_ratelimit_packets;
+ __le64 rx_ratelimit_bytes;
+};
+
+struct virtio_net_stats_tx_speed {
+ struct virtio_net_stats_reply_hdr hdr;
+
+ /* tx_{packets,bytes}_allowance_exceeded are too long. So rename to
+ * short name.
+ */
+ __le64 tx_ratelimit_packets;
+ __le64 tx_ratelimit_bytes;
+};
+
#endif /* _UAPI_LINUX_VIRTIO_NET_H */
diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h
index b1c503c..e878e7c 100644
--- a/riscv/include/asm/kvm.h
+++ b/riscv/include/asm/kvm.h
@@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZFA,
KVM_RISCV_ISA_EXT_ZTSO,
KVM_RISCV_ISA_EXT_ZACAS,
+ KVM_RISCV_ISA_EXT_SSCOFPMF,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/x86/include/asm/kvm.h b/x86/include/asm/kvm.h
index ef11aa4..9fae1b7 100644
--- a/x86/include/asm/kvm.h
+++ b/x86/include/asm/kvm.h
@@ -457,8 +457,13 @@ struct kvm_sync_regs {
#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001
-/* attributes for system fd (group 0) */
-#define KVM_X86_XCOMP_GUEST_SUPP 0
+/* vendor-independent attributes for system fd (group 0) */
+#define KVM_X86_GRP_SYSTEM 0
+# define KVM_X86_XCOMP_GUEST_SUPP 0
+
+/* vendor-specific groups and attributes for system fd */
+#define KVM_X86_GRP_SEV 1
+# define KVM_X86_SEV_VMSA_FEATURES 0
struct kvm_vmx_nested_state_data {
__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
@@ -689,6 +694,9 @@ enum sev_cmd_id {
/* Guest Migration Extension */
KVM_SEV_SEND_CANCEL,
+ /* Second time is the charm; improved versions of the above ioctls. */
+ KVM_SEV_INIT2,
+
KVM_SEV_NR_MAX,
};
@@ -700,6 +708,14 @@ struct kvm_sev_cmd {
__u32 sev_fd;
};
+struct kvm_sev_init {
+ __u64 vmsa_features;
+ __u32 flags;
+ __u16 ghcb_version;
+ __u16 pad1;
+ __u32 pad2[8];
+};
+
struct kvm_sev_launch_start {
__u32 handle;
__u32 policy;
@@ -856,5 +872,7 @@ struct kvm_hyperv_eventfd {
#define KVM_X86_DEFAULT_VM 0
#define KVM_X86_SW_PROTECTED_VM 1
+#define KVM_X86_SEV_VM 2
+#define KVM_X86_SEV_ES_VM 3
#endif /* _ASM_X86_KVM_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [kvmtool PATCH v3 2/4] riscv: Add Sscofpmf extensiona support
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 1/4] Sync-up headers with Linux-6.10 kernel Anup Patel
@ 2024-08-21 14:26 ` Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 3/4] riscv: Set SBI_SUCCESS on successful DBCN call Anup Patel
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2024-08-21 14:26 UTC (permalink / raw)
To: Will Deacon, julien.thierry.kdev, maz
Cc: Paolo Bonzini, Atish Patra, Andrew Jones, Anup Patel, kvm,
kvm-riscv, Atish Patra, Anup Patel
From: Atish Patra <atishp@rivosinc.com>
When the Sscofpmf extension is available expose it to the guest
via device tree so that guest can use it.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/fdt.c | 1 +
riscv/include/kvm/kvm-config-arch.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/riscv/fdt.c b/riscv/fdt.c
index cf367b9..e331f80 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -18,6 +18,7 @@ struct isa_ext_info isa_info_arr[] = {
/* sorted alphabetically */
{"smstateen", KVM_RISCV_ISA_EXT_SMSTATEEN},
{"ssaia", KVM_RISCV_ISA_EXT_SSAIA},
+ {"sscofpmf", KVM_RISCV_ISA_EXT_SSCOFPMF},
{"sstc", KVM_RISCV_ISA_EXT_SSTC},
{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
{"svnapot", KVM_RISCV_ISA_EXT_SVNAPOT},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 17f0ceb..3fbc4f7 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -31,6 +31,9 @@ struct kvm_config_arch {
OPT_BOOLEAN('\0', "disable-ssaia", \
&(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSAIA], \
"Disable Ssaia Extension"), \
+ OPT_BOOLEAN('\0', "disable-sscofpmf", \
+ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSCOFPMF], \
+ "Disable Sscofpmf Extension"), \
OPT_BOOLEAN('\0', "disable-sstc", \
&(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSTC], \
"Disable Sstc Extension"), \
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [kvmtool PATCH v3 3/4] riscv: Set SBI_SUCCESS on successful DBCN call
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 1/4] Sync-up headers with Linux-6.10 kernel Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 2/4] riscv: Add Sscofpmf extensiona support Anup Patel
@ 2024-08-21 14:26 ` Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 4/4] riscv: Correct number of hart bits Anup Patel
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2024-08-21 14:26 UTC (permalink / raw)
To: Will Deacon, julien.thierry.kdev, maz
Cc: Paolo Bonzini, Atish Patra, Andrew Jones, Anup Patel, kvm,
kvm-riscv, Anup Patel
From: Andrew Jones <ajones@ventanamicro.com>
Ensure we explicitly set SBI_SUCCESS on a successful SBI calls
since KVM will not initialize it to zero for us. Only DBCN was
neglecting to do so.
Fixes: 4ddaa4249e0c ("riscv: Handle SBI DBCN calls from Guest/VM")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/kvm-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
index ae87848..0c171da 100644
--- a/riscv/kvm-cpu.c
+++ b/riscv/kvm-cpu.c
@@ -162,6 +162,7 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
switch (vcpu->kvm_run->riscv_sbi.function_id) {
case SBI_EXT_DBCN_CONSOLE_WRITE:
case SBI_EXT_DBCN_CONSOLE_READ:
+ vcpu->kvm_run->riscv_sbi.ret[0] = SBI_SUCCESS;
addr = vcpu->kvm_run->riscv_sbi.args[1];
#if __riscv_xlen == 32
addr |= (u64)vcpu->kvm_run->riscv_sbi.args[2] << 32;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [kvmtool PATCH v3 4/4] riscv: Correct number of hart bits
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
` (2 preceding siblings ...)
2024-08-21 14:26 ` [kvmtool PATCH v3 3/4] riscv: Set SBI_SUCCESS on successful DBCN call Anup Patel
@ 2024-08-21 14:26 ` Anup Patel
2024-08-27 9:46 ` [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-30 16:12 ` Will Deacon
5 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2024-08-21 14:26 UTC (permalink / raw)
To: Will Deacon, julien.thierry.kdev, maz
Cc: Paolo Bonzini, Atish Patra, Andrew Jones, Anup Patel, kvm,
kvm-riscv, Anup Patel
From: Andrew Jones <ajones@ventanamicro.com>
The number of hart bits should be obtained from the highest hart ID,
not the number of harts. For example, if a guest has 2 harts, then
the number of bits should be fls(1) == 1.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/aia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/riscv/aia.c b/riscv/aia.c
index fe9399a..21d9704 100644
--- a/riscv/aia.c
+++ b/riscv/aia.c
@@ -164,7 +164,7 @@ static int aia__init(struct kvm *kvm)
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_nr_sources_attr);
if (ret)
return ret;
- aia_hart_bits = fls_long(kvm->nrcpus);
+ aia_hart_bits = fls_long(kvm->nrcpus - 1);
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_hart_bits_attr);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
` (3 preceding siblings ...)
2024-08-21 14:26 ` [kvmtool PATCH v3 4/4] riscv: Correct number of hart bits Anup Patel
@ 2024-08-27 9:46 ` Anup Patel
2024-08-30 16:12 ` Will Deacon
5 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2024-08-27 9:46 UTC (permalink / raw)
To: Will Deacon, julien.thierry.kdev, maz
Cc: Paolo Bonzini, Atish Patra, Andrew Jones, Anup Patel, kvm,
kvm-riscv
Hi Will,
On Wed, Aug 21, 2024 at 7:56 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> This series adds support for new ISA extensions based on Linux-6.10 namely:
> Sscofpmf.
>
> These patches can also be found in the riscv_more_exts_round3_v3 branch
> at: https://github.com/avpatel/kvmtool.git
>
> Changes since v2:
> - Include a fix to correct number of hart bits for AIA
>
> Changes since v1:
> - Included a fix for DBCN
>
> Andrew Jones (2):
> riscv: Set SBI_SUCCESS on successful DBCN call
> riscv: Correct number of hart bits
>
> Anup Patel (1):
> Sync-up headers with Linux-6.10 kernel
>
> Atish Patra (1):
> riscv: Add Sscofpmf extensiona support
>
> include/linux/kvm.h | 4 +-
> include/linux/virtio_net.h | 143 ++++++++++++++++++++++++++++
> riscv/aia.c | 2 +-
> riscv/fdt.c | 1 +
> riscv/include/asm/kvm.h | 1 +
> riscv/include/kvm/kvm-config-arch.h | 3 +
> riscv/kvm-cpu.c | 1 +
> x86/include/asm/kvm.h | 22 ++++-
> 8 files changed, 172 insertions(+), 5 deletions(-)
Friendly ping !
Regards,
Anup
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
` (4 preceding siblings ...)
2024-08-27 9:46 ` [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
@ 2024-08-30 16:12 ` Will Deacon
5 siblings, 0 replies; 7+ messages in thread
From: Will Deacon @ 2024-08-30 16:12 UTC (permalink / raw)
To: julien.thierry.kdev, maz, Anup Patel
Cc: catalin.marinas, kernel-team, Will Deacon, Paolo Bonzini,
Atish Patra, Andrew Jones, Anup Patel, kvm, kvm-riscv
On Wed, 21 Aug 2024 19:56:06 +0530, Anup Patel wrote:
> This series adds support for new ISA extensions based on Linux-6.10 namely:
> Sscofpmf.
>
> These patches can also be found in the riscv_more_exts_round3_v3 branch
> at: https://github.com/avpatel/kvmtool.git
>
> Changes since v2:
> - Include a fix to correct number of hart bits for AIA
>
> [...]
Applied to kvmtool (master), thanks!
[1/4] Sync-up headers with Linux-6.10 kernel
https://git.kernel.org/will/kvmtool/c/01171537bcc0
[2/4] riscv: Add Sscofpmf extensiona support
https://git.kernel.org/will/kvmtool/c/fa958fb68cfb
[3/4] riscv: Set SBI_SUCCESS on successful DBCN call
https://git.kernel.org/will/kvmtool/c/027784f4c67e
[4/4] riscv: Correct number of hart bits
https://git.kernel.org/will/kvmtool/c/100fade1ac13
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 7+ messages in thread