From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
julien.thierry.kdev@gmail.com, maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [kvmtool PATCH v3 3/4] riscv: Set SBI_SUCCESS on successful DBCN call
Date: Wed, 21 Aug 2024 19:56:09 +0530 [thread overview]
Message-ID: <20240821142610.3297483-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20240821142610.3297483-1-apatel@ventanamicro.com>
From: Andrew Jones <ajones@ventanamicro.com>
Ensure we explicitly set SBI_SUCCESS on a successful SBI calls
since KVM will not initialize it to zero for us. Only DBCN was
neglecting to do so.
Fixes: 4ddaa4249e0c ("riscv: Handle SBI DBCN calls from Guest/VM")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/kvm-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
index ae87848..0c171da 100644
--- a/riscv/kvm-cpu.c
+++ b/riscv/kvm-cpu.c
@@ -162,6 +162,7 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
switch (vcpu->kvm_run->riscv_sbi.function_id) {
case SBI_EXT_DBCN_CONSOLE_WRITE:
case SBI_EXT_DBCN_CONSOLE_READ:
+ vcpu->kvm_run->riscv_sbi.ret[0] = SBI_SUCCESS;
addr = vcpu->kvm_run->riscv_sbi.args[1];
#if __riscv_xlen == 32
addr |= (u64)vcpu->kvm_run->riscv_sbi.args[2] << 32;
--
2.34.1
next prev parent reply other threads:[~2024-08-21 14:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 1/4] Sync-up headers with Linux-6.10 kernel Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 2/4] riscv: Add Sscofpmf extensiona support Anup Patel
2024-08-21 14:26 ` Anup Patel [this message]
2024-08-21 14:26 ` [kvmtool PATCH v3 4/4] riscv: Correct number of hart bits Anup Patel
2024-08-27 9:46 ` [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-30 16:12 ` Will Deacon
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