From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
julien.thierry.kdev@gmail.com, maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [kvmtool PATCH v3 4/4] riscv: Correct number of hart bits
Date: Wed, 21 Aug 2024 19:56:10 +0530 [thread overview]
Message-ID: <20240821142610.3297483-5-apatel@ventanamicro.com> (raw)
In-Reply-To: <20240821142610.3297483-1-apatel@ventanamicro.com>
From: Andrew Jones <ajones@ventanamicro.com>
The number of hart bits should be obtained from the highest hart ID,
not the number of harts. For example, if a guest has 2 harts, then
the number of bits should be fls(1) == 1.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
riscv/aia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/riscv/aia.c b/riscv/aia.c
index fe9399a..21d9704 100644
--- a/riscv/aia.c
+++ b/riscv/aia.c
@@ -164,7 +164,7 @@ static int aia__init(struct kvm *kvm)
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_nr_sources_attr);
if (ret)
return ret;
- aia_hart_bits = fls_long(kvm->nrcpus);
+ aia_hart_bits = fls_long(kvm->nrcpus - 1);
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_hart_bits_attr);
if (ret)
return ret;
--
2.34.1
next prev parent reply other threads:[~2024-08-21 14:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 14:26 [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 1/4] Sync-up headers with Linux-6.10 kernel Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 2/4] riscv: Add Sscofpmf extensiona support Anup Patel
2024-08-21 14:26 ` [kvmtool PATCH v3 3/4] riscv: Set SBI_SUCCESS on successful DBCN call Anup Patel
2024-08-21 14:26 ` Anup Patel [this message]
2024-08-27 9:46 ` [kvmtool PATCH v3 0/4] Add RISC-V ISA extensions based on Linux-6.10 Anup Patel
2024-08-30 16:12 ` Will Deacon
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