From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Josh Poimboeuf <jpoimboe@kernel.org>,
Sandipan Das <sandipan.das@amd.com>,
Kai Huang <kai.huang@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org
Subject: Re: [PATCH v3 1/4] x86/cpufeatures: Clarify semantics of X86_FEATURE_IBPB
Date: Mon, 26 Aug 2024 13:33:08 -0700 [thread overview]
Message-ID: <20240826203308.litigvo6zomwapws@desk> (raw)
In-Reply-To: <20240823185323.2563194-2-jmattson@google.com>
On Fri, Aug 23, 2024 at 11:53:10AM -0700, Jim Mattson wrote:
> Since this synthetic feature bit is set on AMD CPUs that don't flush
> the RSB on an IBPB, indicate as much in the comment, to avoid
> potential confusion with the Intel IBPB semantics.
>
> Signed-off-by: Jim Mattson <jmattson@google.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index dd4682857c12..cabd6b58e8ec 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -215,7 +215,7 @@
> #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */
> #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */
> #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */
> -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */
> +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */
I don't think the comment is accurate for Intel. Maybe you meant to modify
X86_FEATURE_AMD_IBPB?
next prev parent reply other threads:[~2024-08-26 20:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 18:53 [PATCH v3 0/4] Distinguish between variants of IBPB Jim Mattson
2024-08-23 18:53 ` [PATCH v3 1/4] x86/cpufeatures: Clarify semantics of X86_FEATURE_IBPB Jim Mattson
2024-08-26 20:33 ` Pawan Gupta [this message]
2024-08-26 20:59 ` Jim Mattson
2024-08-26 22:28 ` Pawan Gupta
2024-08-23 18:53 ` [PATCH v3 2/4] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET Jim Mattson
2024-08-23 18:53 ` [PATCH v3 3/4] KVM: x86: Advertise AMD_IBPB_RET to userspace Jim Mattson
2024-08-23 18:53 ` [PATCH v3 4/4] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB Jim Mattson
2024-08-23 19:40 ` Tom Lendacky
2024-08-23 20:51 ` Sean Christopherson
2024-08-23 22:00 ` Jim Mattson
2024-08-23 22:12 ` Tom Lendacky
2024-08-23 22:48 ` Jim Mattson
2024-08-23 23:49 ` Jim Mattson
2024-08-29 0:21 ` Sean Christopherson
2024-08-23 19:41 ` [PATCH v3 0/4] Distinguish between variants of IBPB Tom Lendacky
2024-08-25 12:17 ` Thomas Gleixner
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