From: Nikunj A Dadhania <nikunj@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>, <kvm@vger.kernel.org>
Cc: <thomas.lendacky@amd.com>, <santosh.shukla@amd.com>,
<bp@alien8.de>, <ketanch@iitk.ac.in>, <nikunj@amd.com>
Subject: [RFC PATCH 3/5] KVM: SVM: Add GUEST_TSC_FREQ MSR
Date: Thu, 29 Aug 2024 11:07:46 +0530 [thread overview]
Message-ID: <20240829053748.8283-4-nikunj@amd.com> (raw)
In-Reply-To: <20240829053748.8283-1-nikunj@amd.com>
TSC calculation in Secure TSC enabled guests uses a new read-only MSR
0xc0010134 (GUEST_TSC_FREQ). Add the GUEST_TSC_FREQ MSR and disable
the interception when secure TSC is enabled. Moreover, GUEST_TSC_FREQ
MSR is only available to the guest and is not accessible from hypervisor
context.
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kvm/svm/sev.c | 2 ++
arch/x86/kvm/svm/svm.c | 1 +
arch/x86/kvm/svm/svm.h | 2 +-
4 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 82c6a4d350e0..b15635de1290 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -586,6 +586,7 @@
#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
+#define MSR_AMD64_GUEST_TSC_FREQ 0xc0010134
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
#define MSR_AMD_PPIN_CTL 0xc00102f0
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index ff82a644b174..9adab01d9003 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -851,6 +851,8 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm)
save->dr6 = svm->vcpu.arch.dr6;
save->sev_features = sev->vmsa_features;
+ if (save->sev_features & SVM_SEV_FEAT_SECURE_TSC)
+ set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_GUEST_TSC_FREQ, 1, 1);
/*
* Skip FPU and AVX setup with KVM_SEV_ES_INIT to avoid
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index d6f252555ab3..bf86410b2f43 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -142,6 +142,7 @@ static const struct svm_direct_access_msrs {
{ .index = X2APIC_MSR(APIC_TMICT), .always = false },
{ .index = X2APIC_MSR(APIC_TMCCT), .always = false },
{ .index = X2APIC_MSR(APIC_TDCR), .always = false },
+ { .index = MSR_AMD64_GUEST_TSC_FREQ, .always = false },
{ .index = MSR_INVALID, .always = false },
};
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 262b638dfcb8..9d4280d564e9 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -30,7 +30,7 @@
#define IOPM_SIZE PAGE_SIZE * 3
#define MSRPM_SIZE PAGE_SIZE * 2
-#define MAX_DIRECT_ACCESS_MSRS 48
+#define MAX_DIRECT_ACCESS_MSRS 49
#define MSRPM_OFFSETS 32
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
extern bool npt_enabled;
--
2.34.1
next prev parent reply other threads:[~2024-08-29 5:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 5:37 [RFC PATCH 0/5] Enable Secure TSC for SEV-SNP Nikunj A Dadhania
2024-08-29 5:37 ` [RFC PATCH 1/5] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
2024-08-29 13:22 ` Borislav Petkov
2024-09-02 4:16 ` Nikunj A. Dadhania
2024-09-02 16:42 ` Borislav Petkov
2024-09-03 5:43 ` Nikunj A. Dadhania
2024-09-03 7:16 ` Borislav Petkov
2024-08-29 5:37 ` [RFC PATCH 2/5] KVM: SVM: Set TSC frequency for SecureTSC-enabled guests Nikunj A Dadhania
2024-08-29 5:37 ` Nikunj A Dadhania [this message]
2024-08-29 5:37 ` [RFC PATCH 4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled Nikunj A Dadhania
2024-08-29 5:37 ` [RFC PATCH 5/5] KVM: SVM: Add Secure TSC support for SNP Guest Nikunj A Dadhania
2024-11-22 0:41 ` [RFC PATCH 0/5] Enable Secure TSC for SEV-SNP Isaku Yamahata
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