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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Eric Auger <eauger@redhat.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
Subject: [PATCH 14/16] KVM: arm64: nv: Propagate used_lrs between L1 and L0 contexts
Date: Tue, 17 Dec 2024 15:13:29 +0000	[thread overview]
Message-ID: <20241217151331.934077-15-maz@kernel.org> (raw)
In-Reply-To: <20241217151331.934077-1-maz@kernel.org>

We have so far made sure that L1 and L0 vgic contexts were
totally independent. There is however one spot of bother with
this approach, and that's in the GICv3 emulation code required by
our fruity friends.

The issue is that the emulation code needs to know how many LRs
are in flight. And while it is easy to reach the L0 version through
the vcpu pointer, doing so for the L1 is much more complicated,
as these structures are private to the nested code.

We could simply expose that structure and pick one or the other
depending on the context, but this seems extra complexity for not
much benefit.

Instead, just propagate the number of used LRs from the nested code
into the L0 context, and be done with it. Should this become a burden,
it can be easily rectified.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/vgic/vgic-v3-nested.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
index fba499a20aec8..b81bfa85ebb19 100644
--- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
+++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
@@ -323,6 +323,12 @@ void vgic_v3_load_nested(struct kvm_vcpu *vcpu)
 	__vgic_v3_activate_traps(cpu_if);
 
 	__vgic_v3_restore_state(cpu_if);
+
+	/*
+	 * Propagate the number of used LRs for the benefit of the HYP
+	 * GICv3 emulation code. Yes, this is a pretty sorry hack.
+	 */
+	vcpu->arch.vgic_cpu.vgic_v3.used_lrs = cpu_if->used_lrs;
 }
 
 void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
@@ -358,6 +364,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
 	}
 
 	shadow_if->lr_map = 0;
+	vcpu->arch.vgic_cpu.vgic_v3.used_lrs = 0;
 }
 
 /*
-- 
2.39.2


  parent reply	other threads:[~2024-12-17 15:14 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-17 15:13 [PATCH 00/16] KVM: arm64: Add NV GICv3 support Marc Zyngier
2024-12-17 15:13 ` [PATCH 01/16] arm64: sysreg: Add layout for ICH_HCR_EL2 Marc Zyngier
2024-12-17 15:13 ` [PATCH 02/16] arm64: sysreg: Add layout for ICH_VTR_EL2 Marc Zyngier
2024-12-17 15:13 ` [PATCH 03/16] arm64: sysreg: Add layout for ICH_MISR_EL2 Marc Zyngier
2024-12-17 15:13 ` [PATCH 04/16] KVM: arm64: Move host SVE/SME state flags out of vCPU Marc Zyngier
2024-12-17 15:13 ` [PATCH 05/16] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2024-12-17 15:13 ` [PATCH 06/16] KVM: arm64: nv: Add ICH_*_EL2 registers to vpcu_sysreg Marc Zyngier
2024-12-17 15:13 ` [PATCH 07/16] KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses Marc Zyngier
2024-12-17 15:13 ` [PATCH 08/16] KVM: arm64: nv: Sanitise ICH_HCR_EL2 accesses Marc Zyngier
2024-12-17 15:13 ` [PATCH 09/16] KVM: arm64: nv: Nested GICv3 emulation Marc Zyngier
2024-12-17 15:13 ` [PATCH 10/16] KVM: arm64: nv: Handle L2->L1 transition on interrupt injection Marc Zyngier
2024-12-17 15:13 ` [PATCH 11/16] KVM: arm64: nv: Add Maintenance Interrupt emulation Marc Zyngier
2024-12-17 17:38   ` Marc Zyngier
2024-12-17 15:13 ` [PATCH 12/16] KVM: arm64: nv: Respect virtual HCR_EL2.TWx setting Marc Zyngier
2024-12-17 15:13 ` [PATCH 13/16] KVM: arm64: nv: Request vPE doorbell upon nested ERET to L2 Marc Zyngier
2024-12-17 15:13 ` Marc Zyngier [this message]
2024-12-17 15:13 ` [PATCH 15/16] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2024-12-17 15:13 ` [PATCH 16/16] KVM: arm64: nv: Allow userland to set VGIC maintenance IRQ Marc Zyngier

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