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[142.68.128.5]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-46e102fc99asm43201701cf.29.2025.01.20.05.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 05:59:33 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1tZsJR-00000003PaH-1oaY; Mon, 20 Jan 2025 09:59:33 -0400 Date: Mon, 20 Jan 2025 09:59:33 -0400 From: Jason Gunthorpe To: Wencheng Yang Cc: Joerg Roedel , Suravee Suthikulpanit , Will Deacon , Robin Murphy , Alex Williamson , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v2] drviers/iommu/amd: support P2P access through IOMMU when SME is enabled Message-ID: <20250120135933.GJ674319@ziepe.ca> References: <20250117071423.469880-1-east.moutain.yang@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250117071423.469880-1-east.moutain.yang@gmail.com> On Fri, Jan 17, 2025 at 03:14:18PM +0800, Wencheng Yang wrote: > When SME is enabled, memory encryption bit is set in IOMMU page table > pte entry, it works fine if the pfn of the pte entry is memory. > However, if the pfn is MMIO address, for example, map other device's mmio > space to its io page table, in such situation, setting memory encryption > bit in pte would cause P2P failure. This doesn't seem entirely right to me, the encrypted bit should flow in from the entity doing the map and be based on more detailed knowledge about what is happening. Not be guessed at inside the iommu. We have non-encrpyted CPU memory, and (someday) encrypted MMIO. Jason