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From: Andrew Jones <andrew.jones@linux.dev>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	 Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <apatel@ventanamicro.com>,
	 Atish Patra <atishp@rivosinc.com>
Subject: Re: [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests
Date: Thu, 20 Mar 2025 14:40:16 +0100	[thread overview]
Message-ID: <20250320-ab264d08531d4ff10b874485@orel> (raw)
In-Reply-To: <20250317164655.1120015-9-cleger@rivosinc.com>

On Mon, Mar 17, 2025 at 05:46:53PM +0100, Clément Léger wrote:
...
> +	/* Test all flags allowed for SBI_SSE_ATTR_INTERRUPTED_FLAGS */
> +	attr = SBI_SSE_ATTR_INTERRUPTED_FLAGS;
> +	ret = sbi_sse_read_attrs(event_id, attr, 1, &prev_value);
> +	sbiret_report_error(&ret, SBI_SUCCESS, "Save interrupted flags");
> +
> +	for (i = 0; i < ARRAY_SIZE(interrupted_flags); i++) {
> +		flags = interrupted_flags[i];
> +		ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
> +		sbiret_report_error(&ret, SBI_SUCCESS,
> +				    "Set interrupted flags bit 0x%lx value", flags);
> +		ret = sbi_sse_read_attrs(event_id, attr, 1, &value);
> +		sbiret_report_error(&ret, SBI_SUCCESS, "Get interrupted flags after set");
> +		report(value == flags, "interrupted flags modified value: 0x%lx", value);
> +	}
> +
> +	/* Write invalid bit in flag register */
> +	flags = SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT << 1;
> +	ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
> +	sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
> +			    flags);
> +
> +	flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);

This broke compiling for rv32, but just changing it to BIT_ULL wouldn't be
right either since SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT is a BIT().
I think the test just above this one is what this test was aiming to do,
making it redundant. Instead of removing it, I changed it as below to get
more coverage, at least on rv64.

Thanks,
drew

diff --git a/riscv/sbi-sse.c b/riscv/sbi-sse.c
index fb4ee7dd44b2..f9e389728616 100644
--- a/riscv/sbi-sse.c
+++ b/riscv/sbi-sse.c
@@ -495,10 +495,12 @@ static void sse_simple_handler(void *data, struct pt_regs *regs, unsigned int ha
        sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
                            flags);

-       flags = BIT(SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SDT + 1);
+#if __riscv_xlen > 32
+       flags = BIT(32);
        ret = sbi_sse_write_attrs(event_id, attr, 1, &flags);
        sbiret_report_error(&ret, SBI_ERR_INVALID_PARAM, "Set invalid flags bit 0x%lx value error",
                            flags);
+#endif

        ret = sbi_sse_write_attrs(event_id, attr, 1, &prev_value);
        sbiret_report_error(&ret, SBI_SUCCESS, "Restore interrupted flags");

  reply	other threads:[~2025-03-20 13:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-17 16:46 [kvm-unit-tests PATCH v11 0/8] riscv: add SBI SSE extension tests Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 1/8] kbuild: Allow multiple asm-offsets file to be generated Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 2/8] riscv: Set .aux.o files as .PRECIOUS Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 3/8] riscv: Use asm-offsets to generate SBI_EXT_HSM values Clément Léger
2025-03-20 13:36   ` Andrew Jones
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 4/8] lib: riscv: Add functions for version checking Clément Léger
2025-03-19 17:31   ` Andrew Jones
2025-03-20  8:08     ` Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 5/8] lib: riscv: Add functions to get implementer ID and version Clément Léger
2025-03-19 17:36   ` Andrew Jones
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 6/8] riscv: lib: Add SBI SSE extension definitions Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 7/8] lib: riscv: Add SBI SSE support Clément Léger
2025-03-17 16:46 ` [kvm-unit-tests PATCH v11 8/8] riscv: sbi: Add SSE extension tests Clément Léger
2025-03-20 13:40   ` Andrew Jones [this message]
2025-03-20 13:44     ` Clément Léger
2025-03-20 13:46   ` Andrew Jones
2025-03-20 13:50     ` Clément Léger
2025-03-19 18:01 ` [kvm-unit-tests PATCH v11 0/8] riscv: add SBI " Andrew Jones
2025-03-20  8:13   ` Clément Léger
2025-03-20 14:26 ` Andrew Jones
2025-03-22 10:46 ` Andrew Jones

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