From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 156E3286414; Tue, 6 May 2025 16:44:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746549851; cv=none; b=gl6PUUEAKg4Ven3tHVM41nCopmivcppw1R9Qnq2z5dvI3q5d3DozxpEKa82ugJMeWF/161YkFkr9iyM9rM3boYQ04x0XK7TkN8nYLxN9iN/oIn+XU3EOYusAc78KbFO0bDJPdRE67i1rEzVojKbEbi9T5g3kYricslVmpKqQ9jE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746549851; c=relaxed/simple; bh=HVyrhbh/HpF5+b2+bq8685zj0KTE22LyzGPDs5kkaFs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=acRuGDpmkbp91LUOfv4BsommyrXNOuvhWlctXo1CXEVY1eav+R4yhglmlhR+WUsnmEeJIBoJwCha+gDV5sFBhOLczRIvUEc9BfElb1K06ec8PwuEC5efQ6AUSRCjEmCkUG0H5jeLT/vFLkq7/DbfQN5C1WP6E/huS49xGluyLlc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BWBFfsrt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BWBFfsrt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6D53C4CEEB; Tue, 6 May 2025 16:44:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746549850; bh=HVyrhbh/HpF5+b2+bq8685zj0KTE22LyzGPDs5kkaFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BWBFfsrtiFjzMuNRXaKDLdIjgg96U6RKSeD2h0BQfyQWt9Okv/N7EcqpIKt3eVAiU ppYrQ6AsVBurYzSfHYiix0L+iDyq3RoyvJ4QAIOjoz7YuDuhNSTaNNmgScGgNsSDD1 8W/TZlRpR0EcK6xx5mDyeaj75OukEJM7QCZlzoUTIgm8Nq0sI8lT0msAkQ3g8/0ozO YV96cQBt2aEh/HH6hMgyAgHYiJ4Y1M3w0CYL5caZgij1haYelwy0hMKAt7sbTmb37i RyLPiakfGcQtfcFD6F6tn43qqHVnMninkADuJkUADDCeRg3KlOodUl9Nz04XgNZRmK C8aWsLuuslHYA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uCLOr-00CJkN-74; Tue, 06 May 2025 17:44:09 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba , Will Deacon , Catalin Marinas , Ben Horgan Subject: [PATCH v4 14/43] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Date: Tue, 6 May 2025 17:43:19 +0100 Message-Id: <20250506164348.346001-15-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250506164348.346001-1-maz@kernel.org> References: <20250506164348.346001-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com, will@kernel.org, catalin.marinas@arm.com, ben.horgan@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Provide the architected EC and ISS values for all the FEAT_LS64* instructions. Reviewed-by: Joey Gouly Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/esr.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index e4f77757937e6..a0ae66dd65da9 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -20,7 +20,8 @@ #define ESR_ELx_EC_FP_ASIMD UL(0x07) #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ -/* Unallocated EC: 0x0A - 0x0B */ +#define ESR_ELx_EC_OTHER UL(0x0A) +/* Unallocated EC: 0x0B */ #define ESR_ELx_EC_CP14_64 UL(0x0C) #define ESR_ELx_EC_BTI UL(0x0D) #define ESR_ELx_EC_ILL UL(0x0E) @@ -181,6 +182,11 @@ #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) +/* ISS definitions for LD64B/ST64B instructions */ +#define ESR_ELx_ISS_OTHER_ST64BV (0) +#define ESR_ELx_ISS_OTHER_ST64BV0 (1) +#define ESR_ELx_ISS_OTHER_LDST64B (2) + #define DISR_EL1_IDS (UL(1) << 24) /* * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean -- 2.39.2