From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Fuad Tabba <tabba@google.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Ben Horgan <ben.horgan@arm.com>
Subject: [PATCH v4 23/43] KVM: arm64: Add description of FGT bits leading to EC!=0x18
Date: Tue, 6 May 2025 17:43:28 +0100 [thread overview]
Message-ID: <20250506164348.346001-24-maz@kernel.org> (raw)
In-Reply-To: <20250506164348.346001-1-maz@kernel.org>
The current FTP tables are only concerned with the bits generating
ESR_ELx.EC==0x18. However, we want an exhaustive view of what KVM
really knows about.
So let's add another small table that provides that extra information.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/emulate-nested.c | 36 +++++++++++++++++++++++++++------
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 528b33fcfcfd6..c30d970bf81cb 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1279,16 +1279,21 @@ enum fg_filter_id {
__NR_FG_FILTER_IDS__
};
-#define SR_FGF(sr, g, b, p, f) \
- { \
- .encoding = sr, \
- .end = sr, \
- .tc = { \
+#define __FGT(g, b, p, f) \
+ { \
.fgt = g ## _GROUP, \
.bit = g ## _EL2_ ## b ## _SHIFT, \
.pol = p, \
.fgf = f, \
- }, \
+ }
+
+#define FGT(g, b, p) __FGT(g, b, p, __NO_FGF__)
+
+#define SR_FGF(sr, g, b, p, f) \
+ { \
+ .encoding = sr, \
+ .end = sr, \
+ .tc = __FGT(g, b, p, f), \
.line = __LINE__, \
}
@@ -1989,6 +1994,18 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1),
};
+/*
+ * Additional FGTs that do not fire with ESR_EL2.EC==0x18. This table
+ * isn't used for exception routing, but only as a promise that the
+ * trap is handled somewhere else.
+ */
+static const union trap_config non_0x18_fgt[] __initconst = {
+ FGT(HFGITR, nGCSSTR_EL1, 0),
+ FGT(HFGITR, SVC_EL1, 1),
+ FGT(HFGITR, SVC_EL0, 1),
+ FGT(HFGITR, ERET, 1),
+};
+
static union trap_config get_trap_config(u32 sysreg)
{
return (union trap_config) {
@@ -2203,6 +2220,13 @@ int __init populate_nv_trap_config(void)
}
}
+ for (int i = 0; i < ARRAY_SIZE(non_0x18_fgt); i++) {
+ if (!aggregate_fgt(non_0x18_fgt[i])) {
+ ret = -EINVAL;
+ kvm_err("non_0x18_fgt[%d] is reserved\n", i);
+ }
+ }
+
ret = check_all_fgt_masks(ret);
kvm_info("nv: %ld fine grained trap handlers\n",
--
2.39.2
next prev parent reply other threads:[~2025-05-06 16:44 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-06 16:43 [PATCH v4 00/43] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 01/43] arm64: sysreg: Add ID_AA64ISAR1_EL1.LS64 encoding for FEAT_LS64WB Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 02/43] arm64: sysreg: Update ID_AA64MMFR4_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 03/43] arm64: sysreg: Add layout for HCR_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 04/43] arm64: sysreg: Replace HFGxTR_EL2 with HFG{R,W}TR_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 05/43] arm64: sysreg: Update ID_AA64PFR0_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 06/43] arm64: sysreg: Update PMSIDR_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 07/43] arm64: sysreg: Update TRBIDR_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 08/43] arm64: sysreg: Update CPACR_EL1 description Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 09/43] arm64: sysreg: Add registers trapped by HFG{R,W}TR2_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 10/43] arm64: sysreg: Add registers trapped by HDFG{R,W}TR2_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 11/43] arm64: sysreg: Add system instructions trapped by HFGIRT2_EL2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 12/43] arm64: Remove duplicated sysreg encodings Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 13/43] arm64: tools: Resync sysreg.h Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 14/43] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 15/43] arm64: Add FEAT_FGT2 capability Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 16/43] KVM: arm64: Tighten handling of unknown FGT groups Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 17/43] KVM: arm64: Simplify handling of negative FGT bits Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 18/43] KVM: arm64: Handle trapping of FEAT_LS64* instructions Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 19/43] KVM: arm64: Restrict ACCDATA_EL1 undef to FEAT_LS64_ACCDATA being disabled Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 20/43] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 21/43] KVM: arm64: Plug FEAT_GCS handling Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 22/43] KVM: arm64: Compute FGT masks from KVM's own FGT tables Marc Zyngier
2025-05-06 16:43 ` Marc Zyngier [this message]
2025-05-06 16:43 ` [PATCH v4 24/43] KVM: arm64: Use computed masks as sanitisers for FGT registers Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 25/43] KVM: arm64: Unconditionally configure fine-grain traps Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 26/43] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 27/43] KVM: arm64: Use computed FGT masks to setup FGT registers Marc Zyngier
2025-05-08 13:49 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 28/43] KVM: arm64: Remove hand-crafted masks for " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 29/43] KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 30/43] KVM: arm64: Handle PSB CSYNC traps Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 31/43] KVM: arm64: Switch to table-driven FGU configuration Marc Zyngier
2025-05-08 15:58 ` Joey Gouly
2025-05-10 9:56 ` Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 32/43] KVM: arm64: Validate FGT register descriptions against RES0 masks Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 33/43] KVM: arm64: Use FGT feature maps to drive RES0 bits Marc Zyngier
2025-05-15 15:24 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 34/43] KVM: arm64: Allow kvm_has_feat() to take variable arguments Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 35/43] KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 36/43] KVM: arm64: Use HCR_EL2 " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 37/43] KVM: arm64: Add FEAT_FGT2 registers to the VNCR page Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 38/43] KVM: arm64: Add sanitisation for FEAT_FGT2 registers Marc Zyngier
2025-05-15 16:04 ` Joey Gouly
2025-05-06 16:43 ` [PATCH v4 39/43] KVM: arm64: Add trap routing " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 40/43] KVM: arm64: Add context-switch " Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 41/43] KVM: arm64: Allow sysreg ranges for FGT descriptors Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 42/43] KVM: arm64: Add FGT descriptors for FEAT_FGT2 Marc Zyngier
2025-05-06 16:43 ` [PATCH v4 43/43] KVM: arm64: Handle TSB CSYNC traps Marc Zyngier
2025-05-19 11:59 ` [PATCH v4 00/43] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
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