From: Atish Patra <atishp@rivosinc.com>
To: Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Mayuresh Chitale <mchitale@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Atish Patra <atishp@rivosinc.com>
Subject: [PATCH v3 1/9] drivers/perf: riscv: Add SBI v3.0 flag
Date: Thu, 22 May 2025 12:03:35 -0700 [thread overview]
Message-ID: <20250522-pmu_event_info-v3-1-f7bba7fd9cfe@rivosinc.com> (raw)
In-Reply-To: <20250522-pmu_event_info-v3-0-f7bba7fd9cfe@rivosinc.com>
There are new PMU related features introduced in SBI v3.0.
1. Raw Event v2 which allows mhpmeventX value to be 56 bit wide.
2. Get Event info function to do a bulk query at one shot.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
drivers/perf/riscv_pmu_sbi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 698de8ddf895..cfd6946fca42 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -63,6 +63,7 @@ PMU_FORMAT_ATTR(event, "config:0-47");
PMU_FORMAT_ATTR(firmware, "config:62-63");
static bool sbi_v2_available;
+static bool sbi_v3_available;
static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
#define sbi_pmu_snapshot_available() \
static_branch_unlikely(&sbi_pmu_snapshot_available)
@@ -1452,6 +1453,9 @@ static int __init pmu_sbi_devinit(void)
if (sbi_spec_version >= sbi_mk_version(2, 0))
sbi_v2_available = true;
+ if (sbi_spec_version >= sbi_mk_version(3, 0))
+ sbi_v3_available = true;
+
ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
"perf/riscv/pmu:starting",
pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
--
2.43.0
next prev parent reply other threads:[~2025-05-22 19:03 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-22 19:03 [PATCH v3 0/9] Add SBI v3.0 PMU enhancements Atish Patra
2025-05-22 19:03 ` Atish Patra [this message]
2025-07-17 15:11 ` [PATCH v3 1/9] drivers/perf: riscv: Add SBI v3.0 flag Anup Patel
2025-05-22 19:03 ` [PATCH v3 2/9] drivers/perf: riscv: Add raw event v2 support Atish Patra
2025-07-17 15:17 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 3/9] RISC-V: KVM: Add support for Raw event v2 Atish Patra
2025-07-17 15:18 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 4/9] drivers/perf: riscv: Implement PMU event info function Atish Patra
2025-07-18 4:32 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 5/9] drivers/perf: riscv: Export " Atish Patra
2025-07-18 4:39 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 6/9] KVM: Add a helper function to validate vcpu gpa range Atish Patra
2025-07-17 16:04 ` Anup Patel
2025-07-17 16:07 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 7/9] RISC-V: KVM: Use the new gpa range validate helper function Atish Patra
2025-07-18 4:40 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 8/9] RISC-V: KVM: Implement get event info function Atish Patra
2025-07-18 5:44 ` Anup Patel
2025-05-22 19:03 ` [PATCH v3 9/9] RISC-V: KVM: Upgrade the supported SBI version to 3.0 Atish Patra
2025-05-23 13:31 ` Radim Krčmář
2025-05-23 17:16 ` Atish Patra
2025-05-26 9:00 ` Radim Krčmář
2025-05-26 11:13 ` Andrew Jones
2025-05-28 14:16 ` Atish Patra
2025-05-28 15:09 ` Andrew Jones
2025-05-28 19:21 ` Atish Patra
2025-05-29 1:17 ` Atish Patra
2025-05-29 10:24 ` Radim Krčmář
2025-05-29 18:44 ` Atish Patra
2025-05-29 19:14 ` Andrew Jones
2025-05-30 11:45 ` Anup Patel
2025-05-30 11:09 ` Radim Krčmář
2025-05-30 19:29 ` Atish Patra
2025-06-03 11:40 ` Radim Krčmář
2025-06-04 0:29 ` Atish Patra
2025-07-18 4:44 ` Anup Patel
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