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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2eceb9711asm6306066a12.57.2025.06.03.08.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 08:47:09 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Jones , Ved Shanbhogue Subject: [kvm-unit-tests v2 0/2] riscv: Add double trap testing Date: Tue, 3 Jun 2025 17:46:48 +0200 Message-ID: <20250603154652.1712459-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a test that triggers double trap and verify that it's behavior conforms to the spec. Also use SSE to verify that an SSE event is correctly sent upon double trap. In order to run this test, one can use the following command using an upstream version of OpenSBI: $ QEMU=qemu-system-riscv64 \ FIRMWARE_OVERRIDE=/fw_dynamic.bin \ ./riscv-run riscv/isa-dbltrp.flat --- v2: - Use WRITE_ONCE/READ_ONCE for shared variables - Remove locking flag for last test - Fix a few typos - Skip crash test if env var DOUBLE_TRAP_TEST_CRASH isn't set - Skip crash test if SSE event unregistering failed - Remove SDT clearing patch - Fix wrong check using ret.value nstead of ret.error Clément Léger (2): lib/riscv: export FWFT functions riscv: Add ISA double trap extension testing riscv/Makefile | 1 + lib/riscv/asm/csr.h | 1 + lib/riscv/asm/processor.h | 10 ++ lib/riscv/asm/sbi.h | 5 + lib/riscv/sbi.c | 20 ++++ riscv/isa-dbltrp.c | 211 ++++++++++++++++++++++++++++++++++++++ riscv/sbi-fwft.c | 49 +++------ riscv/unittests.cfg | 4 + 8 files changed, 266 insertions(+), 35 deletions(-) create mode 100644 riscv/isa-dbltrp.c -- 2.49.0