From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3315C13B2A4 for ; Fri, 6 Jun 2025 08:32:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749198761; cv=none; b=TLCQxtDSrR2Z5FFTkls39xci+EWQ03v2VGqaSrWQy0ruybPblR67jZxCb6XQ8AEnAY4h03zJAgUujNd3TSGpMBz6soWlAlUFRqLouHeh43rNcXArur/bEPlk86pbxsYXQl5Bxqm/7Wa9P7TZZOHw6TirF1jmhRSxSgN7kC8nCvk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749198761; c=relaxed/simple; bh=sGVTNIGiiw0Q76mM1YYrcKY/BTZdy/REejIJnpFL6qg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=JTZDHqHLbjJK6MHgjLM2woSiLix1GxQgv5iE9lG/9N+vcmUZeDYDRAKhZtOS7WwsXu9/cUpMYpqBVVNi8VlAc8XELb+mBji984RSDE+/P4zesMJVmJIZGy+TzC/KTm6xWglWtUoXehFO4xXHU3ck8pPzyLcOWq2K9u4ZAimNITI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=NjqVhN+d; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="NjqVhN+d" Date: Fri, 6 Jun 2025 10:32:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1749198746; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=0rjnQ5h06Wz4/Zf1hGvZjWlBwp2Qnw/DkUpb5h4A7oE=; b=NjqVhN+dZVzSxuBLk3run4PObbEVNl1Iw0rPv+HzYy9qcJ5Pjc/MNaf13ZNPI4zlS+8LPp ZMJOXfMZdaD4H7McYYSNoXMSzf9Lqf0EpF5xgqsElSgtogzW10NORVlbeFe/HA7Cs6yStN z+M4H84O26vYwfLlQDxe6GDB1sCdfpY= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Andrew Jones To: Jesse Taube Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Atish Patra , Anup Patel , Palmer Dabbelt , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Himanshu Chauhan , Charlie Jenkins Subject: Re: [kvm-unit-tests PATCH v3 1/2] riscv: Add RV_INSN_LEN to processor.h Message-ID: <20250606-cbdb324240e2de802f08d32c@orel> References: <20250605161806.1206850-1-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250605161806.1206850-1-jesse@rivosinc.com> X-Migadu-Flow: FLOW_OUT On Thu, Jun 05, 2025 at 09:18:05AM -0700, Jesse Taube wrote: > When handeling traps and faults it is offten necessary to know the size handling often > of the instruction at epc. Add RV_INSN_LEN to calculate the > instruction size. > > Signed-off-by: Jesse Taube > --- > lib/riscv/asm/processor.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h > index 40104272..631ce226 100644 > --- a/lib/riscv/asm/processor.h > +++ b/lib/riscv/asm/processor.h > @@ -7,6 +7,8 @@ > #define EXCEPTION_CAUSE_MAX 24 > #define INTERRUPT_CAUSE_MAX 16 > > +#define RV_INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4) > + > typedef void (*exception_fn)(struct pt_regs *); > > struct thread_info { > -- > 2.43.0 > I've fixed the two typos while applying to riscv/sbi[1] [1] https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi Thanks, drew > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv