* [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
@ 2025-06-17 13:10 ` zhouquan
2025-06-20 9:36 ` Nutty Liu
2025-06-24 13:45 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM zhouquan
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: zhouquan @ 2025-06-17 13:10 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
We're about to allow guests to use the Zicbop extension.
KVM userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 5f59fd226cc5..0863ca178066 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -55,6 +55,7 @@ struct kvm_riscv_config {
unsigned long mimpid;
unsigned long zicboz_block_size;
unsigned long satp_mode;
+ unsigned long zicbop_block_size;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 2e1b646f0d61..b08a22eaa7a7 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -256,6 +256,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -ENOENT;
reg_val = riscv_cboz_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
+ if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
+ return -ENOENT;
+ reg_val = riscv_cbop_block_size;
+ break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
reg_val = vcpu->arch.mvendorid;
break;
@@ -347,6 +352,12 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
if (reg_val != riscv_cboz_block_size)
return -EINVAL;
break;
+ case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
+ if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
+ return -ENOENT;
+ if (reg_val != riscv_cbop_block_size)
+ return -EINVAL;
+ break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
if (reg_val == vcpu->arch.mvendorid)
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size
2025-06-17 13:10 ` [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size zhouquan
@ 2025-06-20 9:36 ` Nutty Liu
2025-06-24 13:45 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Nutty Liu @ 2025-06-20 9:36 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> We're about to allow guests to use the Zicbop extension.
> KVM userspace needs to know the cache block size in order to
> properly advertise it to the guest. Provide a virtual config
> register for userspace to get it with the GET_ONE_REG API, but
> setting it cannot be supported, so disallow SET_ONE_REG.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 11 +++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 5f59fd226cc5..0863ca178066 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -55,6 +55,7 @@ struct kvm_riscv_config {
> unsigned long mimpid;
> unsigned long zicboz_block_size;
> unsigned long satp_mode;
> + unsigned long zicbop_block_size;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 2e1b646f0d61..b08a22eaa7a7 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -256,6 +256,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -ENOENT;
> reg_val = riscv_cboz_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
> + return -ENOENT;
> + reg_val = riscv_cbop_block_size;
> + break;
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> reg_val = vcpu->arch.mvendorid;
> break;
> @@ -347,6 +352,12 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> if (reg_val != riscv_cboz_block_size)
> return -EINVAL;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
> + return -ENOENT;
> + if (reg_val != riscv_cbop_block_size)
Seems "riscv_cbop_block_size" has not been declared.
Otherwise,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
> + return -EINVAL;
> + break;
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> if (reg_val == vcpu->arch.mvendorid)
> break;
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size
2025-06-17 13:10 ` [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size zhouquan
2025-06-20 9:36 ` Nutty Liu
@ 2025-06-24 13:45 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Andrew Jones @ 2025-06-24 13:45 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 09:10:22PM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> We're about to allow guests to use the Zicbop extension.
> KVM userspace needs to know the cache block size in order to
> properly advertise it to the guest. Provide a virtual config
> register for userspace to get it with the GET_ONE_REG API, but
> setting it cannot be supported, so disallow SET_ONE_REG.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 11 +++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 5f59fd226cc5..0863ca178066 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -55,6 +55,7 @@ struct kvm_riscv_config {
> unsigned long mimpid;
> unsigned long zicboz_block_size;
> unsigned long satp_mode;
> + unsigned long zicbop_block_size;
> };
>
> /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 2e1b646f0d61..b08a22eaa7a7 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -256,6 +256,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> return -ENOENT;
> reg_val = riscv_cboz_block_size;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
I realize this is the same as what we do for zicbom and zicboz, but I
think we should actually check riscv_isa_extension_available(NULL, ZICBOP)
instead. The reason is that we otherwise create an ioctl order dependency
on the VMM.
I suggest adding a patch to this series, which would come first, to change
zicbom and zicboz block size registers to depend on the host, not the
guest, isa. The patch should also change the reg list filtering in
copy_config_reg_indices() to use the host isa. And then this patch should
change to also use the host isa. Also, this patch is missing the reg list
filtering for zicbop, so it should be added too.
Thanks,
drew
> + return -ENOENT;
> + reg_val = riscv_cbop_block_size;
> + break;
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> reg_val = vcpu->arch.mvendorid;
> break;
> @@ -347,6 +352,12 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> if (reg_val != riscv_cboz_block_size)
> return -EINVAL;
> break;
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOP))
> + return -ENOENT;
> + if (reg_val != riscv_cbop_block_size)
> + return -EINVAL;
> + break;
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> if (reg_val == vcpu->arch.mvendorid)
> break;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
2025-06-17 13:10 ` [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size zhouquan
@ 2025-06-17 13:10 ` zhouquan
2025-06-20 9:40 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 3/5] RISC-V: KVM: Allow bfloat16 " zhouquan
` (3 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: zhouquan @ 2025-06-17 13:10 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zicbop extension for Guest/VM.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 0863ca178066..56959d277e86 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -185,6 +185,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZICCRSE,
KVM_RISCV_ISA_EXT_ZAAMO,
KVM_RISCV_ISA_EXT_ZALRSC,
+ KVM_RISCV_ISA_EXT_ZICBOP,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index b08a22eaa7a7..d444ec9e9e8e 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -68,6 +68,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZFH),
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
+ KVM_ISA_EXT_ARR(ZICBOP),
KVM_ISA_EXT_ARR(ZICBOZ),
KVM_ISA_EXT_ARR(ZICCRSE),
KVM_ISA_EXT_ARR(ZICNTR),
@@ -171,6 +172,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_ZFA:
case KVM_RISCV_ISA_EXT_ZFH:
case KVM_RISCV_ISA_EXT_ZFHMIN:
+ case KVM_RISCV_ISA_EXT_ZICBOP:
case KVM_RISCV_ISA_EXT_ZICCRSE:
case KVM_RISCV_ISA_EXT_ZICNTR:
case KVM_RISCV_ISA_EXT_ZICOND:
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM
2025-06-17 13:10 ` [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM zhouquan
@ 2025-06-20 9:40 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Nutty Liu @ 2025-06-20 9:40 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zicbop extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 0863ca178066..56959d277e86 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -185,6 +185,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZICCRSE,
> KVM_RISCV_ISA_EXT_ZAAMO,
> KVM_RISCV_ISA_EXT_ZALRSC,
> + KVM_RISCV_ISA_EXT_ZICBOP,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index b08a22eaa7a7..d444ec9e9e8e 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -68,6 +68,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> + KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> @@ -171,6 +172,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZFA:
> case KVM_RISCV_ISA_EXT_ZFH:
> case KVM_RISCV_ISA_EXT_ZFHMIN:
> + case KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_RISCV_ISA_EXT_ZICOND:
Seems 'RISCV_ISA_EXT_ZICBOP' should be declared in 'arch/riscv/include/asm/hwcap.h' ?
Otherwise,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM
2025-06-17 13:10 ` [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM zhouquan
2025-06-20 9:40 ` Nutty Liu
@ 2025-06-24 13:46 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Andrew Jones @ 2025-06-24 13:46 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 09:10:30PM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zicbop extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 0863ca178066..56959d277e86 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -185,6 +185,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZICCRSE,
> KVM_RISCV_ISA_EXT_ZAAMO,
> KVM_RISCV_ISA_EXT_ZALRSC,
> + KVM_RISCV_ISA_EXT_ZICBOP,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index b08a22eaa7a7..d444ec9e9e8e 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -68,6 +68,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> + KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> @@ -171,6 +172,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZFA:
> case KVM_RISCV_ISA_EXT_ZFH:
> case KVM_RISCV_ISA_EXT_ZFHMIN:
> + case KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_RISCV_ISA_EXT_ZICOND:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/5] RISC-V: KVM: Allow bfloat16 extension for Guest/VM
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
2025-06-17 13:10 ` [PATCH 1/5] RISC-V: KVM: Provide UAPI for Zicbop block size zhouquan
2025-06-17 13:10 ` [PATCH 2/5] RISC-V: KVM: Allow Zicbop extension for Guest/VM zhouquan
@ 2025-06-17 13:10 ` zhouquan
2025-06-20 9:49 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test zhouquan
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: zhouquan @ 2025-06-17 13:10 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zfbmin/Zvfbfmin/Zvfbfwma extension for Guest/VM.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 3 +++
arch/riscv/kvm/vcpu_onereg.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 56959d277e86..79a5ac86597c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -186,6 +186,9 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZAAMO,
KVM_RISCV_ISA_EXT_ZALRSC,
KVM_RISCV_ISA_EXT_ZICBOP,
+ KVM_RISCV_ISA_EXT_ZFBFMIN,
+ KVM_RISCV_ISA_EXT_ZVFBFMIN,
+ KVM_RISCV_ISA_EXT_ZVFBFWMA,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index d444ec9e9e8e..2ba3f2c942ee 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -65,6 +65,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZCF),
KVM_ISA_EXT_ARR(ZCMOP),
KVM_ISA_EXT_ARR(ZFA),
+ KVM_ISA_EXT_ARR(ZFBFMIN),
KVM_ISA_EXT_ARR(ZFH),
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
@@ -89,6 +90,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZTSO),
KVM_ISA_EXT_ARR(ZVBB),
KVM_ISA_EXT_ARR(ZVBC),
+ KVM_ISA_EXT_ARR(ZVFBFMIN),
+ KVM_ISA_EXT_ARR(ZVFBFWMA),
KVM_ISA_EXT_ARR(ZVFH),
KVM_ISA_EXT_ARR(ZVFHMIN),
KVM_ISA_EXT_ARR(ZVKB),
@@ -170,6 +173,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_ZCF:
case KVM_RISCV_ISA_EXT_ZCMOP:
case KVM_RISCV_ISA_EXT_ZFA:
+ case KVM_RISCV_ISA_EXT_ZFBFMIN:
case KVM_RISCV_ISA_EXT_ZFH:
case KVM_RISCV_ISA_EXT_ZFHMIN:
case KVM_RISCV_ISA_EXT_ZICBOP:
@@ -192,6 +196,8 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_ZTSO:
case KVM_RISCV_ISA_EXT_ZVBB:
case KVM_RISCV_ISA_EXT_ZVBC:
+ case KVM_RISCV_ISA_EXT_ZVFBFMIN:
+ case KVM_RISCV_ISA_EXT_ZVFBFWMA:
case KVM_RISCV_ISA_EXT_ZVFH:
case KVM_RISCV_ISA_EXT_ZVFHMIN:
case KVM_RISCV_ISA_EXT_ZVKB:
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/5] RISC-V: KVM: Allow bfloat16 extension for Guest/VM
2025-06-17 13:10 ` [PATCH 3/5] RISC-V: KVM: Allow bfloat16 " zhouquan
@ 2025-06-20 9:49 ` Nutty Liu
2025-06-24 13:46 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Nutty Liu @ 2025-06-20 9:49 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zfbmin/Zvfbfmin/Zvfbfwma extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu_onereg.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 56959d277e86..79a5ac86597c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -186,6 +186,9 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZAAMO,
> KVM_RISCV_ISA_EXT_ZALRSC,
> KVM_RISCV_ISA_EXT_ZICBOP,
> + KVM_RISCV_ISA_EXT_ZFBFMIN,
> + KVM_RISCV_ISA_EXT_ZVFBFMIN,
> + KVM_RISCV_ISA_EXT_ZVFBFWMA,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index d444ec9e9e8e..2ba3f2c942ee 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -65,6 +65,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZCF),
> KVM_ISA_EXT_ARR(ZCMOP),
> KVM_ISA_EXT_ARR(ZFA),
> + KVM_ISA_EXT_ARR(ZFBFMIN),
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> @@ -89,6 +90,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZTSO),
> KVM_ISA_EXT_ARR(ZVBB),
> KVM_ISA_EXT_ARR(ZVBC),
> + KVM_ISA_EXT_ARR(ZVFBFMIN),
> + KVM_ISA_EXT_ARR(ZVFBFWMA),
> KVM_ISA_EXT_ARR(ZVFH),
> KVM_ISA_EXT_ARR(ZVFHMIN),
> KVM_ISA_EXT_ARR(ZVKB),
> @@ -170,6 +173,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZCF:
> case KVM_RISCV_ISA_EXT_ZCMOP:
> case KVM_RISCV_ISA_EXT_ZFA:
> + case KVM_RISCV_ISA_EXT_ZFBFMIN:
> case KVM_RISCV_ISA_EXT_ZFH:
> case KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_RISCV_ISA_EXT_ZICBOP:
> @@ -192,6 +196,8 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZTSO:
> case KVM_RISCV_ISA_EXT_ZVBB:
> case KVM_RISCV_ISA_EXT_ZVBC:
> + case KVM_RISCV_ISA_EXT_ZVFBFMIN:
> + case KVM_RISCV_ISA_EXT_ZVFBFWMA:
> case KVM_RISCV_ISA_EXT_ZVFH:
> case KVM_RISCV_ISA_EXT_ZVFHMIN:
> case KVM_RISCV_ISA_EXT_ZVKB:
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 3/5] RISC-V: KVM: Allow bfloat16 extension for Guest/VM
2025-06-17 13:10 ` [PATCH 3/5] RISC-V: KVM: Allow bfloat16 " zhouquan
2025-06-20 9:49 ` Nutty Liu
@ 2025-06-24 13:46 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Andrew Jones @ 2025-06-24 13:46 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 09:10:35PM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zfbmin/Zvfbfmin/Zvfbfwma extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 3 +++
> arch/riscv/kvm/vcpu_onereg.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 56959d277e86..79a5ac86597c 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -186,6 +186,9 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZAAMO,
> KVM_RISCV_ISA_EXT_ZALRSC,
> KVM_RISCV_ISA_EXT_ZICBOP,
> + KVM_RISCV_ISA_EXT_ZFBFMIN,
> + KVM_RISCV_ISA_EXT_ZVFBFMIN,
> + KVM_RISCV_ISA_EXT_ZVFBFWMA,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index d444ec9e9e8e..2ba3f2c942ee 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -65,6 +65,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZCF),
> KVM_ISA_EXT_ARR(ZCMOP),
> KVM_ISA_EXT_ARR(ZFA),
> + KVM_ISA_EXT_ARR(ZFBFMIN),
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> @@ -89,6 +90,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZTSO),
> KVM_ISA_EXT_ARR(ZVBB),
> KVM_ISA_EXT_ARR(ZVBC),
> + KVM_ISA_EXT_ARR(ZVFBFMIN),
> + KVM_ISA_EXT_ARR(ZVFBFWMA),
> KVM_ISA_EXT_ARR(ZVFH),
> KVM_ISA_EXT_ARR(ZVFHMIN),
> KVM_ISA_EXT_ARR(ZVKB),
> @@ -170,6 +173,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZCF:
> case KVM_RISCV_ISA_EXT_ZCMOP:
> case KVM_RISCV_ISA_EXT_ZFA:
> + case KVM_RISCV_ISA_EXT_ZFBFMIN:
> case KVM_RISCV_ISA_EXT_ZFH:
> case KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_RISCV_ISA_EXT_ZICBOP:
> @@ -192,6 +196,8 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZTSO:
> case KVM_RISCV_ISA_EXT_ZVBB:
> case KVM_RISCV_ISA_EXT_ZVBC:
> + case KVM_RISCV_ISA_EXT_ZVFBFMIN:
> + case KVM_RISCV_ISA_EXT_ZVFBFWMA:
> case KVM_RISCV_ISA_EXT_ZVFH:
> case KVM_RISCV_ISA_EXT_ZVFHMIN:
> case KVM_RISCV_ISA_EXT_ZVKB:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
` (2 preceding siblings ...)
2025-06-17 13:10 ` [PATCH 3/5] RISC-V: KVM: Allow bfloat16 " zhouquan
@ 2025-06-17 13:10 ` zhouquan
2025-06-20 9:58 ` Nutty Liu
2025-06-24 13:47 ` Andrew Jones
2025-06-17 13:10 ` [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 " zhouquan
2025-07-17 12:04 ` [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest Anup Patel
5 siblings, 2 replies; 17+ messages in thread
From: zhouquan @ 2025-06-17 13:10 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
The KVM RISC-V allows Zicbop extension for Guest/VM
so add them to get-reg-list test.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index a0b7dabb5040..ebdc34b58bad 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -83,6 +83,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
@@ -253,6 +254,8 @@ static const char *config_id_to_str(const char *prefix, __u64 id)
return "KVM_REG_RISCV_CONFIG_REG(isa)";
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
+ case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
+ return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
@@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(ZFH),
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
+ KVM_ISA_EXT_ARR(ZICBOP),
KVM_ISA_EXT_ARR(ZICBOZ),
KVM_ISA_EXT_ARR(ZICCRSE),
KVM_ISA_EXT_ARR(ZICNTR),
@@ -864,6 +868,11 @@ static __u64 zicbom_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
};
+static __u64 zicbop_regs[] = {
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
+};
+
static __u64 zicboz_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
@@ -1012,6 +1021,8 @@ static __u64 vector_regs[] = {
.regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
#define SUBLIST_ZICBOM \
{"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
+#define SUBLIST_ZICBOP \
+ {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
#define SUBLIST_ZICBOZ \
{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
#define SUBLIST_AIA \
@@ -1130,6 +1141,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
+KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
@@ -1204,6 +1216,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_zfh,
&config_zfhmin,
&config_zicbom,
+ &config_zicbop,
&config_zicboz,
&config_ziccrse,
&config_zicntr,
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test
2025-06-17 13:10 ` [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test zhouquan
@ 2025-06-20 9:58 ` Nutty Liu
2025-06-24 13:47 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Nutty Liu @ 2025-06-20 9:58 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Zicbop extension for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index a0b7dabb5040..ebdc34b58bad 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -83,6 +83,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
> @@ -253,6 +254,8 @@ static const char *config_id_to_str(const char *prefix, __u64 id)
> return "KVM_REG_RISCV_CONFIG_REG(isa)";
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> @@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> + KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> @@ -864,6 +868,11 @@ static __u64 zicbom_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
> };
>
> +static __u64 zicbop_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
> +};
> +
> static __u64 zicboz_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
> @@ -1012,6 +1021,8 @@ static __u64 vector_regs[] = {
> .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
> #define SUBLIST_ZICBOM \
> {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
> +#define SUBLIST_ZICBOP \
> + {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
> #define SUBLIST_ZICBOZ \
> {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
> #define SUBLIST_AIA \
> @@ -1130,6 +1141,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> +KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
> @@ -1204,6 +1216,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zfh,
> &config_zfhmin,
> &config_zicbom,
> + &config_zicbop,
> &config_zicboz,
> &config_ziccrse,
> &config_zicntr,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test
2025-06-17 13:10 ` [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test zhouquan
2025-06-20 9:58 ` Nutty Liu
@ 2025-06-24 13:47 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Andrew Jones @ 2025-06-24 13:47 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 09:10:42PM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Zicbop extension for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index a0b7dabb5040..ebdc34b58bad 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -83,6 +83,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
> @@ -253,6 +254,8 @@ static const char *config_id_to_str(const char *prefix, __u64 id)
> return "KVM_REG_RISCV_CONFIG_REG(isa)";
> case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
> + case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
> + return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
> return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
> case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> @@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> + KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> @@ -864,6 +868,11 @@ static __u64 zicbom_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
> };
>
> +static __u64 zicbop_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
> +};
> +
> static __u64 zicboz_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
> @@ -1012,6 +1021,8 @@ static __u64 vector_regs[] = {
> .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
> #define SUBLIST_ZICBOM \
> {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
> +#define SUBLIST_ZICBOP \
> + {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
> #define SUBLIST_ZICBOZ \
> {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
> #define SUBLIST_AIA \
> @@ -1130,6 +1141,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> +KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
> @@ -1204,6 +1216,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zfh,
> &config_zfhmin,
> &config_zicbom,
> + &config_zicbop,
> &config_zicboz,
> &config_ziccrse,
> &config_zicntr,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 extension to get-reg-list test
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
` (3 preceding siblings ...)
2025-06-17 13:10 ` [PATCH 4/5] KVM: riscv: selftests: Add Zicbop extension to get-reg-list test zhouquan
@ 2025-06-17 13:10 ` zhouquan
2025-06-20 9:58 ` Nutty Liu
2025-06-24 13:47 ` Andrew Jones
2025-07-17 12:04 ` [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest Anup Patel
5 siblings, 2 replies; 17+ messages in thread
From: zhouquan @ 2025-06-17 13:10 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
The KVM RISC-V allows Zfbfmin/Zvfbfmin/Zvfbfwma extensions for Guest/VM
so add them to get-reg-list test.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index ebdc34b58bad..e5a07e000b66 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -80,6 +80,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
@@ -104,6 +105,8 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
@@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(ZCF),
KVM_ISA_EXT_ARR(ZCMOP),
KVM_ISA_EXT_ARR(ZFA),
+ KVM_ISA_EXT_ARR(ZFBFMIN),
KVM_ISA_EXT_ARR(ZFH),
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
@@ -559,6 +563,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(ZTSO),
KVM_ISA_EXT_ARR(ZVBB),
KVM_ISA_EXT_ARR(ZVBC),
+ KVM_ISA_EXT_ARR(ZVFBFMIN),
+ KVM_ISA_EXT_ARR(ZVFBFWMA),
KVM_ISA_EXT_ARR(ZVFH),
KVM_ISA_EXT_ARR(ZVFHMIN),
KVM_ISA_EXT_ARR(ZVKB),
@@ -1138,6 +1144,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
+KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
@@ -1162,6 +1169,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);
KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
+KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN);
+KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA);
KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
@@ -1213,6 +1222,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_zcf,
&config_zcmop,
&config_zfa,
+ &config_zfbfmin,
&config_zfh,
&config_zfhmin,
&config_zicbom,
@@ -1237,6 +1247,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_ztso,
&config_zvbb,
&config_zvbc,
+ &config_zvfbfmin,
+ &config_zvfbfwma,
&config_zvfh,
&config_zvfhmin,
&config_zvkb,
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 extension to get-reg-list test
2025-06-17 13:10 ` [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 " zhouquan
@ 2025-06-20 9:58 ` Nutty Liu
2025-06-24 13:47 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Nutty Liu @ 2025-06-20 9:58 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv
On 6/17/2025 9:10 PM, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Zfbfmin/Zvfbfmin/Zvfbfwma extensions for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index ebdc34b58bad..e5a07e000b66 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -80,6 +80,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> @@ -104,6 +105,8 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
> @@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZCF),
> KVM_ISA_EXT_ARR(ZCMOP),
> KVM_ISA_EXT_ARR(ZFA),
> + KVM_ISA_EXT_ARR(ZFBFMIN),
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> @@ -559,6 +563,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZTSO),
> KVM_ISA_EXT_ARR(ZVBB),
> KVM_ISA_EXT_ARR(ZVBC),
> + KVM_ISA_EXT_ARR(ZVFBFMIN),
> + KVM_ISA_EXT_ARR(ZVFBFWMA),
> KVM_ISA_EXT_ARR(ZVFH),
> KVM_ISA_EXT_ARR(ZVFHMIN),
> KVM_ISA_EXT_ARR(ZVKB),
> @@ -1138,6 +1144,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
> KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
> KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> @@ -1162,6 +1169,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
> KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
> @@ -1213,6 +1222,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zcf,
> &config_zcmop,
> &config_zfa,
> + &config_zfbfmin,
> &config_zfh,
> &config_zfhmin,
> &config_zicbom,
> @@ -1237,6 +1247,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_ztso,
> &config_zvbb,
> &config_zvbc,
> + &config_zvfbfmin,
> + &config_zvfbfwma,
> &config_zvfh,
> &config_zvfhmin,
> &config_zvkb,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 extension to get-reg-list test
2025-06-17 13:10 ` [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 " zhouquan
2025-06-20 9:58 ` Nutty Liu
@ 2025-06-24 13:47 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Andrew Jones @ 2025-06-24 13:47 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 09:10:50PM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Zfbfmin/Zvfbfmin/Zvfbfwma extensions for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index ebdc34b58bad..e5a07e000b66 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -80,6 +80,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> @@ -104,6 +105,8 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
> @@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZCF),
> KVM_ISA_EXT_ARR(ZCMOP),
> KVM_ISA_EXT_ARR(ZFA),
> + KVM_ISA_EXT_ARR(ZFBFMIN),
> KVM_ISA_EXT_ARR(ZFH),
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> @@ -559,6 +563,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZTSO),
> KVM_ISA_EXT_ARR(ZVBB),
> KVM_ISA_EXT_ARR(ZVBC),
> + KVM_ISA_EXT_ARR(ZVFBFMIN),
> + KVM_ISA_EXT_ARR(ZVFBFWMA),
> KVM_ISA_EXT_ARR(ZVFH),
> KVM_ISA_EXT_ARR(ZVFHMIN),
> KVM_ISA_EXT_ARR(ZVKB),
> @@ -1138,6 +1144,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
> KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
> KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> @@ -1162,6 +1169,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
> KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
> KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
> @@ -1213,6 +1222,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zcf,
> &config_zcmop,
> &config_zfa,
> + &config_zfbfmin,
> &config_zfh,
> &config_zfhmin,
> &config_zicbom,
> @@ -1237,6 +1247,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_ztso,
> &config_zvbb,
> &config_zvbc,
> + &config_zvfbfmin,
> + &config_zvfbfwma,
> &config_zvfh,
> &config_zvfhmin,
> &config_zvkb,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest
2025-06-17 13:10 [PATCH 0/5] RISC-V: KVM: Allow zicop/bfloat16 exts for guest zhouquan
` (4 preceding siblings ...)
2025-06-17 13:10 ` [PATCH 5/5] KVM: riscv: selftests: Add bfloat16 " zhouquan
@ 2025-07-17 12:04 ` Anup Patel
5 siblings, 0 replies; 17+ messages in thread
From: Anup Patel @ 2025-07-17 12:04 UTC (permalink / raw)
To: zhouquan
Cc: ajones, atishp, paul.walmsley, palmer, linux-kernel, linux-riscv,
kvm, kvm-riscv
On Tue, Jun 17, 2025 at 6:48 PM <zhouquan@iscas.ac.cn> wrote:
>
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Advertise zicop/bfloat16 extensions to KVM guest when underlying
> host supports it, and add them to get-reg-list test.
>
> Quan Zhou (5):
> RISC-V: KVM: Provide UAPI for Zicbop block size
> RISC-V: KVM: Allow Zicbop extension for Guest/VM
> RISC-V: KVM: Allow bfloat16 extension for Guest/VM
> KVM: riscv: selftests: Add Zicbop extension to get-reg-list test
> KVM: riscv: selftests: Add bfloat16 extension to get-reg-list test
Please send v2 of this series addressing Drew's comments.
Regards,
Anup
^ permalink raw reply [flat|nested] 17+ messages in thread