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From: Andrew Jones To: Jesse Taube Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Atish Patra , Anup Patel , Palmer Dabbelt , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Himanshu Chauhan , Charlie Jenkins Subject: Re: [kvm-unit-tests PATCH v8] riscv: sbi: Add SBI Debug Triggers Extension tests Message-ID: <20250702-f6f3fde8cfecdb6901edfc76@orel> References: <20250701200047.1367077-1-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250701200047.1367077-1-jesse@rivosinc.com> X-Migadu-Flow: FLOW_OUT On Tue, Jul 01, 2025 at 01:00:47PM -0700, Jesse Taube wrote: > +#define SBI_DBTR_TDATA1_TYPE_SHIFT (__riscv_xlen - 4) I just double checked and see that this shift is 4 less than xlen, so... > +enum McontrolType { > + SBI_DBTR_TDATA1_TYPE_NONE = (0UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_LEGACY = (1UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_MCONTROL = (2UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_ICOUNT = (3UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_ITRIGGER = (4UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_ETRIGGER = (5UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_MCONTROL6 = (6UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_TMEXTTRIGGER = (7UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_RESERVED0 = (8UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_RESERVED1 = (9UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_RESERVED2 = (10UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_RESERVED3 = (11UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_CUSTOM0 = (12UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_CUSTOM1 = (13UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_CUSTOM2 = (14UL << SBI_DBTR_TDATA1_TYPE_SHIFT), > + SBI_DBTR_TDATA1_TYPE_DISABLED = (15UL << SBI_DBTR_TDATA1_TYPE_SHIFT), ...all these will require unsigned long (as the UL's provide), but that means... > +static unsigned long gen_tdata1(enum McontrolType type, enum Tdata1Value value, enum Tdata1Mode mode) > +{ > + switch (type) { > + case SBI_DBTR_TDATA1_TYPE_MCONTROL: > + return gen_tdata1_mcontrol(mode, value) | mcontrol_size(SIZE_32BIT); > + case SBI_DBTR_TDATA1_TYPE_MCONTROL6: > + return gen_tdata1_mcontrol6(mode, value) | mcontrol6_size(SIZE_32BIT); > + default: > + assert_msg(false, "Invalid mcontrol type: %u", (int)type); ...my suggestion here was wrong for rv64. We need assert_msg(false, "Invalid mcontrol type: %lu", (unsigned long)type); I've fixed it up while applying to riscv/sbi https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi Thanks, drew