From: Zhao Liu <zhao1.liu@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eduardo Habkost" <eduardo@habkost.net>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Babu Moger" <babu.moger@amd.com>,
"Ewan Hai" <ewanhai-oc@zhaoxin.com>, "Pu Wen" <puwen@hygon.cn>,
"Tao Su" <tao1.su@intel.com>, "Yi Lai" <yi1.lai@intel.com>,
"Dapeng Mi" <dapeng1.mi@intel.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Zhao Liu" <zhao1.liu@intel.com>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>
Subject: [PATCH v2 02/18] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding
Date: Fri, 11 Jul 2025 18:21:27 +0800 [thread overview]
Message-ID: <20250711102143.1622339-3-zhao1.liu@intel.com> (raw)
In-Reply-To: <20250711102143.1622339-1-zhao1.liu@intel.com>
The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative,
64 byte line size) corresponds to descriptor 0x49, but at present
cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has
multiple meanings.
The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent
cache model, and use legacy_l2_cache as the default L2 cache.
Therefore, add descriptor 0x49 to represent general L2 cache.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes Since v2:
* Fix the typo in comment. (Dapeng)
---
target/i386/cpu.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6983b5f70457..75932579542a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -127,7 +127,18 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
.associativity = 8, .line_size = 64, },
[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
.associativity = 12, .line_size = 64, },
- /* Descriptor 0x49 depends on CPU family/model, so it is not included */
+ /*
+ * Descriptor 0x49 has 2 cases:
+ * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
+ * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
+ * (Intel Xeon processor MP, Family 0FH, Model 06H).
+ *
+ * When it represents L3, then it depends on CPU family/model. Fortunately,
+ * the legacy cache/CPU models don't have such special L3. So, just add it
+ * to represent the general L2 case.
+ */
+ [0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB,
+ .associativity = 16, .line_size = 64, },
[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 12, .line_size = 64, },
[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
--
2.34.1
next prev parent reply other threads:[~2025-07-11 10:00 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-11 10:21 [PATCH v2 00/18] i386/cpu: Unify the cache model in X86CPUState Zhao Liu
2025-07-11 10:21 ` [PATCH v2 01/18] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Zhao Liu
2025-07-11 10:21 ` Zhao Liu [this message]
2025-07-11 10:21 ` [PATCH v2 03/18] i386/cpu: Add default cache model for Intel CPUs with level < 4 Zhao Liu
2025-07-14 2:14 ` Mi, Dapeng
2025-07-11 10:21 ` [PATCH v2 04/18] i386/cpu: Present same cache model in CPUID 0x2 & 0x4 Zhao Liu
2025-07-11 10:21 ` [PATCH v2 05/18] i386/cpu: Consolidate CPUID 0x4 leaf Zhao Liu
2025-07-11 10:21 ` [PATCH v2 06/18] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState Zhao Liu
2025-07-11 10:21 ` [PATCH v2 07/18] i386/cpu: Add x-vendor-cpuid-only-v2 option for compatibility Zhao Liu
2025-07-11 10:21 ` [PATCH v2 08/18] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Zhao Liu
2025-07-11 10:21 ` [PATCH v2 09/18] i386/cpu: Rename AMD_ENC_ASSOC to X86_ENC_ASSOC Zhao Liu
2025-07-11 10:21 ` [PATCH v2 10/18] i386/cpu: Fix CPUID[0x80000006] for Intel CPU Zhao Liu
2025-07-11 10:21 ` [PATCH v2 11/18] i386/cpu: Add legacy_intel_cache_info cache model Zhao Liu
2025-07-11 10:21 ` [PATCH v2 12/18] i386/cpu: Add legacy_amd_cache_info " Zhao Liu
2025-07-11 10:21 ` [PATCH v2 13/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x2 Zhao Liu
2025-07-11 10:21 ` [PATCH v2 14/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x4 Zhao Liu
2025-07-11 10:21 ` [PATCH v2 15/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005 Zhao Liu
2025-07-11 10:21 ` [PATCH v2 16/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006 Zhao Liu
2025-07-11 10:21 ` [PATCH v2 17/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D Zhao Liu
2025-07-11 10:21 ` [PATCH v2 18/18] i386/cpu: Use a unified cache_info in X86CPUState Zhao Liu
2025-07-11 17:45 ` [PATCH v2 00/18] i386/cpu: Unify the cache model " Paolo Bonzini
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