From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91F523504D for ; Thu, 14 Aug 2025 15:56:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755186991; cv=none; b=f88ZMD0A/xb1sW11+T89FAODPoKXE+/LTqjZ/7oHOGi5TfK7sTvw+3ydf3Xc9uBGD7tgjMQLoV7nUhahZk6z5cE45ItD1R3WavdYja9BHl19E4mNzv26FfLCrtpijcCYOt00ZzG0cxP7JXXfe+JkRU6WyWpGMiUgGHf2xrSFBm8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755186991; c=relaxed/simple; bh=pOWZZ1yAolvhQ4qPW38kR3SL9AJb1VbT0Ng7NeaENQM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RmgvuesxBnOGqxAs6WmOwxnfAucQuB+muRgSMee5hyAkV7BwpWumOBG4nvFRwWsMLN/PFnJ4RS+bKucjEGqjbESDDtJMtKLN/mOJeB/5RZbiq5OU1Ggvuc6ECozPvZz1OYN/bO6lInjXrYlIJVX1Bbg7bHe2mG4LdTOnHi793D8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=cXo7Zr2U; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="cXo7Zr2U" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-323266b6ff5so766051a91.0 for ; Thu, 14 Aug 2025 08:56:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1755186989; x=1755791789; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Svq7qseUrNtldzbZ0qzqJnQgBxG3tF3m1Pv4UZc1zUI=; b=cXo7Zr2UUreGQbmiy/pZucQ89c5uQ3PXtGXLyyHSdOwNTI9fEsXzLukCZIe7RJqFM9 mFO4+1tY3chXD/BbK9qcAohDgKAmxspwpX08IkDOuOKNjQuJoWLg/KSeW3rFZSGCQPEY CpBVlBehzaXs+JMVayVzhCxwnQ7mVFipO/GwBQuEOSGS/GoX+pwezuLyi3VwzQSAtJw+ tn9+H/pUDOz/XQjVW1uDJguvhLDJdkJcxOtBSInykkiw+wak9JRVwNKs2TQEqkTfMLl4 YyV98dW/v/tCrxmHGa+mzftYUyWzkT/r64rXhCTB167Q01k2ZGavr5ib60j7JWIYZTJq vQwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755186989; x=1755791789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Svq7qseUrNtldzbZ0qzqJnQgBxG3tF3m1Pv4UZc1zUI=; b=WQsf8wQWbAROQ8xAP1WJdtoZH6jhnDYnAoZxf46NPmRPB7cgJZcRHF6OH7OJ+u2hKX yCHj1UU1Kbh1VfsajNJ2tpg9SkpfVjqmVWQTs8CAbRp2iKq1Ptl1Z5/yfNk93j0rmbSx Y0EYSBKWPIACDczufG+XadBySp2ybOu+kwWlHbCwznFaVPN69D+gC2KWwl5IpIhOQYiy 35GBF1NEXsAeWyoRAZxD07W4l3b7qZF+rbKsIM0sy/bxcIUEVsEPomy/HZS1bmbBpIkX fxcStAkMoy9hquufT2GVkAq8UEyqhjT6+Kc57q5LGwrHxoyzOLeC2vjLyYvq3+u4m3+N hPaw== X-Forwarded-Encrypted: i=1; AJvYcCUBWizkbat1ahOeqWGgtit4d+5OOdBhlvyUu3U61rdKMCg997UEpnSUpoLkbEhoeerxNCk=@vger.kernel.org X-Gm-Message-State: AOJu0Yz/vJJRIsEfjwSHwdGUCtz1Djyp6XISmfEA1+oSCPLhAkPKN0TS aH+2lj5SlyzYz9Hv2piPG5Yp5jDUO59SRh245Km/KHgGE2osWdQmUqb5Tfm6RZnctHQ= X-Gm-Gg: ASbGnctBSw3X/850T4KkaibCBhHLjx1x/h5wu1qJwp79ku3hfuzSdEtksMgZZQR1K84 FzZUSMfxUvH7iB2iDnPd3kwS11knc2Wu7fnP4a1U+51ZKgIWJWmArNM0g09kP+LGY4pnptCSn2r LCuIQio9Rg9FBeusEvx1ZyGbMG9l9e1iMVfu9UvibmgFxwL8A31P+cUjfQeAwKE6DljGDpaUeyZ ubuSrgzg6rjXR5RzvBIWvweumU1mGlJ+dxpZGd4jXdL3/kgpVWkr+J4RcwGs0aEW8DLyDA5FNMT 5TnZm/lG5UaBltv7DtSRuAhAQ0QZmOM0gA7IgNtxFFb71LZlV2GlNgO2Ws8WG4lM1p87JjdTaOb sMS059m4ktrcn2sHySyYo2TizMeitXLtxJQ6AllXR8yUTYoPHIxd7bHDIaqpmrRJZ10l2PnRE X-Google-Smtp-Source: AGHT+IHWMmf5xN+1nUuUZiP9NZI9A2OjHQdZYcHTdLM60KutAKjF+UXZWVbDMBBXW8FB6v09Xkb8yg== X-Received: by 2002:a17:90b:4990:b0:31f:ecf:36f with SMTP id 98e67ed59e1d1-3232969ad39mr5129703a91.1.1755186988804; Thu, 14 Aug 2025 08:56:28 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3233108e1d9sm2225500a91.29.2025.08.14.08.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Aug 2025 08:56:28 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Date: Thu, 14 Aug 2025 21:25:47 +0530 Message-ID: <20250814155548.457172-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com> References: <20250814155548.457172-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The KVM user-space needs a way to save/restore the state of SBI FWFT features so implement SBI extension ONE_REG callbacks. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 14 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 169 +++++++++++++++++++++++++++--- 2 files changed, 171 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index a5ca0f4ce2d3..fc5624e89c7b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -215,6 +215,17 @@ struct kvm_riscv_sbi_sta { unsigned long shmem_hi; }; +struct kvm_riscv_sbi_fwft_feature { + unsigned long flags; + unsigned long value; +}; + +/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sbi_fwft { + struct kvm_riscv_sbi_fwft_feature misaligned_deleg; + struct kvm_riscv_sbi_fwft_feature pointer_masking; +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -298,6 +309,9 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_SBI_STA_REG(name) \ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_FWFT_REG(name) \ + (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) /* Device Control API: RISC-V AIA */ #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 5a3bad0f9330..0d740e7c5713 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -22,6 +22,11 @@ struct kvm_sbi_fwft_feature { */ enum sbi_fwft_feature_t id; + /** + * @flags_reg_num: ONE_REG index of the feature flag + */ + unsigned long flags_reg_num; + /** * @supported: Check if the feature is supported on the vcpu * @@ -44,7 +49,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsigned long value); + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value); /** * @get: Get the feature current value @@ -53,7 +59,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsigned long *value); + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value); }; static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] = { @@ -91,16 +98,18 @@ static void kvm_sbi_fwft_reset_misaligned_delegation(struct kvm_vcpu *vcpu) static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; if (value == 1) { cfg->hedeleg |= MIS_DELEG; - csr_set(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_set(CSR_HEDELEG, MIS_DELEG); } else if (value == 0) { cfg->hedeleg &= ~MIS_DELEG; - csr_clear(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_clear(CSR_HEDELEG, MIS_DELEG); } else { return SBI_ERR_INVALID_PARAM; } @@ -110,10 +119,11 @@ static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { - *value = (csr_read(CSR_HEDELEG) & MIS_DELEG) == MIS_DELEG; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; + *value = (cfg->hedeleg & MIS_DELEG) == MIS_DELEG; return SBI_SUCCESS; } @@ -145,7 +155,7 @@ static void kvm_sbi_fwft_reset_pointer_masking_pmlen(struct kvm_vcpu *vcpu) static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_sbi_fwft *fwft = vcpu_to_fwft(vcpu); unsigned long pmm; @@ -167,14 +177,15 @@ static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, * update here so that VCPU see's pointer masking mode change * immediately. */ - csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + if (!one_reg_access) + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); return SBI_SUCCESS; } static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { switch (vcpu->arch.cfg.henvcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_0: @@ -198,6 +209,8 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, static const struct kvm_sbi_fwft_feature features[] = { { .id = SBI_FWFT_MISALIGNED_EXC_DELEG, + .flags_reg_num = offsetof(struct kvm_riscv_sbi_fwft, misaligned_deleg.flags) / + sizeof(unsigned long), .supported = kvm_sbi_fwft_misaligned_delegation_supported, .reset = kvm_sbi_fwft_reset_misaligned_delegation, .set = kvm_sbi_fwft_set_misaligned_delegation, @@ -206,6 +219,8 @@ static const struct kvm_sbi_fwft_feature features[] = { #ifndef CONFIG_32BIT { .id = SBI_FWFT_POINTER_MASKING_PMLEN, + .flags_reg_num = offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.flags) / + sizeof(unsigned long), .supported = kvm_sbi_fwft_pointer_masking_pmlen_supported, .reset = kvm_sbi_fwft_reset_pointer_masking_pmlen, .set = kvm_sbi_fwft_set_pointer_masking_pmlen, @@ -214,6 +229,21 @@ static const struct kvm_sbi_fwft_feature features[] = { #endif }; +static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(unsigned long reg_num) +{ + const struct kvm_sbi_fwft_feature *feature; + int i; + + for (i = 0; i < ARRAY_SIZE(features); i++) { + feature = &features[i]; + if (feature->flags_reg_num == reg_num || + (feature->flags_reg_num + 1) == reg_num) + return feature; + } + + return NULL; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t feature) { @@ -267,7 +297,7 @@ static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 feature, conf->flags = flags; - return conf->feature->set(vcpu, conf, value); + return conf->feature->set(vcpu, conf, false, value); } static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, @@ -280,7 +310,7 @@ static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, if (ret) return ret; - return conf->feature->get(vcpu, conf, value); + return conf->feature->get(vcpu, conf, false, value); } static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, @@ -354,6 +384,115 @@ static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *vcpu) } } +static unsigned long kvm_sbi_ext_fwft_get_reg_count(struct kvm_vcpu *vcpu) +{ + unsigned long max_reg_count = sizeof(struct kvm_riscv_sbi_fwft) / sizeof(unsigned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long reg, ret = 0; + + for (reg = 0; reg < max_reg_count; reg++) { + feature = kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf = kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + ret++; + } + + return ret; +} + +static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu *vcpu, int index, u64 *reg_id) +{ + int reg, max_reg_count = sizeof(struct kvm_riscv_sbi_fwft) / sizeof(unsigned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int idx = 0; + + for (reg = 0; reg < max_reg_count; reg++) { + feature = kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf = kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + if (index == idx) { + *reg_id = KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + KVM_REG_RISCV_SBI_FWFT | reg; + return 0; + } + + idx++; + } + + return -ENOENT; +} + +static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long *value; + int ret = 0; + + if (reg_size != sizeof(unsigned long)) + return -EINVAL; + value = reg_val; + + feature = kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf = kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num == reg_num) + *value = conf->flags; + else + ret = conf->feature->get(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + +static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, const void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long value; + int ret = 0; + + if (reg_size != sizeof(unsigned long)) + return -EINVAL; + value = *(const unsigned long *)reg_val; + + feature = kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf = kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num == reg_num) + conf->flags = value & SBI_FWFT_SET_FLAG_LOCK; + else + ret = conf->feature->set(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = { .extid_start = SBI_EXT_FWFT, .extid_end = SBI_EXT_FWFT, @@ -361,4 +500,10 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = { .init = kvm_sbi_ext_fwft_init, .deinit = kvm_sbi_ext_fwft_deinit, .reset = kvm_sbi_ext_fwft_reset, + .have_state = true, + .state_reg_subtype = KVM_REG_RISCV_SBI_FWFT, + .get_state_reg_count = kvm_sbi_ext_fwft_get_reg_count, + .get_state_reg_id = kvm_sbi_ext_fwft_get_reg_id, + .get_state_reg = kvm_sbi_ext_fwft_get_reg, + .set_state_reg = kvm_sbi_ext_fwft_set_reg, }; -- 2.43.0